Texas Instruments TAS2505 Evaluation Module TAS2505EVM TAS2505EVM 数据表
产品代码
TAS2505EVM
t
td
S
ta
MSB OUT
BIT 6 . . . 1
LSB OUT
t
sck
t
Lead
t
Lag
t
sckh
t
sckl
t
r
t
f
t
v(DOUT)
t
dis
MSB IN
BIT 6 . . . 1
LSB IN
t
hi
t
su
SS
SCLK
MISO
MOSI
SLAS778A – FEBRUARY 2013 – REVISED FEBRUARY 2013
3.5.6
SPI Interface Timing
Figure 3-6. SPI Interface Timing Diagram
Timing Requirements
At 25°C, DVDD = 1.8V
Table 3-1. SPI Interface Timing
PARAMETER
TEST CONDITION
IOVDD=1.8V
IOVDD=3.3V
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
t
sck
SCLK Period
(1)
100
50
ns
t
sckh
SCLK Pulse width High
50
25
ns
t
sckl
SCLK Pulse width Low
50
25
ns
t
lead
Enable Lead Time
30
20
ns
t
lag
Enable Lag Time
30
20
ns
t
d
Sequential Transfer Delay
40
20
ns
t
a
Slave DOUT access time
40
40
ns
t
dis
Slave DOUT disable time
40
40
ns
t
su
DIN data setup time
15
15
ns
t
hi
DIN data hold time
15
10
ns
t
v;DOUT
DOUT data valid time
25
18
ns
t
r
SCLK Rise Time
4
4
ns
t
f
SCLK Fall Time
4
4
ns
(1)
These parameters are based on characterization and are not tested in production.
14
ELECTRICAL SPECIFICATIONS
Copyright © 2013, Texas Instruments Incorporated
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