Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM 数据表
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
8.34 Isochronous Cycle Timer Register
The isochronous cycle timer register indicates the current cycle number and offset. When the controller is
cycle master, this register is transmitted with the cycle start message. When the controller is not cycle
master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start
message is not received, the fields can continue incrementing on their own (if programmed) to maintain a
local time reference. See
cycle master, this register is transmitted with the cycle start message. When the controller is not cycle
master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start
message is not received, the fields can continue incrementing on their own (if programmed) to maintain a
local time reference. See
for a complete description of the register contents.
OHCI register offset:
F0h
Register type:
Read/Write/Update
Default value:
XXXX XXXXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Table 8-26. Isochronous Cycle Timer Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31-25
cycleSeconds
RWU
Cycle seconds. This field counts seconds [rollovers from bits 24-12 (cycleCount field)] modulo 128.
24-12
cycleCount
RWU
Cycle count. This field counts cycles [rollovers from bits 11-0 (cycleOffset field)] modulo 8000.
11-0
cycleOffset
RWU
Cycle offset. This field counts 24.576-MHz clocks modulo 3072, that is, 125 s. If an external 8-kHz
clock configuration is being used, this field must be cleared to 000h at each tick of the external clock.
clock configuration is being used, this field must be cleared to 000h at each tick of the external clock.
8.35 Asynchronous Request Filter High Register
The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-
node basis, and handles the upper node IDs. When a packet is destined for either the physical request
context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is
not set to 1b in this register, the packet is not acknowledged and the request is not queued. The node ID
comparison is done if the source node is on the same bus as the controller. Nonlocal bus-sourced packets
are not acknowledged unless bit 31 in this register is set to 1b. See
node basis, and handles the upper node IDs. When a packet is destined for either the physical request
context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is
not set to 1b in this register, the packet is not acknowledged and the request is not queued. The node ID
comparison is done if the source node is on the same bus as the controller. Nonlocal bus-sourced packets
are not acknowledged unless bit 31 in this register is set to 1b. See
for a complete description
of the register contents.
OHCI register offset:
100h set register
104 h clear register
104 h clear register
Register type:
Read/Set/Clear
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
160
1394 OHCI Memory-Mapped Register Space
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