数据表 (XIO2213BEVM)目录Table of Contents21 Introduction121.1 XIO2213B Features122 Overview132.1 Related Documents142.2 Documents Conventions152.3 Ordering Information152.4 Terminal Assignments162.5 Terminal Descriptions243 Feature/Protocol Descriptions313.1 Power-Up/Power-Down Sequencing313.1.1 Power-Up Sequence323.1.2 Power-Down Sequence333.2 XIO2213B Reset Features343.3 PCI Express (PCIe) Interface353.3.1 External Reference Clock353.3.2 Beacon and Wake353.3.3 Initial Flow Control Credits353.3.4 PCIe Message Transactions363.4 PCI Interrupt Conversion to PCIe Messages373.5 Two-Wire Serial-Bus Interface383.5.1 Serial-Bus Interface Implementation383.5.2 Serial-Bus Interface Protocol393.5.3 Serial-Bus EEPROM Application413.5.4 Accessing Serial-Bus Devices Through Softwaree433.6 Advanced Error Reporting Registers433.7 Data Error Forwarding Capability433.8 General-Purpose I/O (GPIO) Interface443.9 Set Slot Power Limit Functionality443.10 PCIe and PCI Bus Power Management443.11 1394b OHCI Controller Functionality463.11.1 1394b OHCI Power Management463.11.2 1394b OHCI and V AUX463.11.3 1394b OHCI and Reset Options463.11.4 1394b OHCI PCI Bus Master463.11.5 1394b OHCI Subsystem Identification473.11.6 1394b OHCI PME Support474 Classic PCI Configuration Space484.1 Vendor ID Register494.2 Device ID Register494.3 Command Register494.4 Status Register514.5 Class Code and Revision ID Register524.6 Cache Line Size Register524.7 Primary Latency Timer Register524.8 Header Type Register534.9 BIST Register534.10 Device Control Base Address Register534.11 Scratchpad RAM Base Address544.12 Primary Bus Number Register544.13 Secondary Bus Number Register544.14 Subordinate Bus Number Register554.15 Secondary Latency Timer Register554.16 I/O Base Register554.17 I/O Limit Register564.18 Secondary Status Register574.19 Memory Base Register584.20 Memory Limit Register584.21 Prefetchable Memory Base Register594.22 Prefetchable Memory Limit Register594.23 Prefetchable Base Upper 32 Bits Register604.24 Prefetchable Limit Upper 32 Bits Register604.25 I/O Base Upper 16 Bits Register614.26 I/O Limit Upper 16 Bits Register614.27 Capabilities Pointer Register624.28 Interrupt Line Register624.29 Interrupt Pin Register624.30 Bridge Control Register634.31 PM Capability ID Register654.32 Next Item Pointer Register654.33 Power Management Capabilities Register664.34 Power Management Control/Status Register674.35 Power Management Bridge Support Extension Register684.36 Power Management Data Register684.37 MSI Capability ID Register684.38 Next Item Pointer Register694.39 MSI Message Control Register694.40 MSI Message Lower Address Register704.41 MSI Message Upper Address Register704.42 MSI Message Data Register714.43 SSID/SSVID Capability ID Register714.44 Next Item Pointer Register714.45 Subsystem Vendor ID Register724.46 Subsystem ID Register724.47 PCI Express Capability ID Register724.48 Next Item Pointer Register724.49 PCI Express Capabilities Register734.50 Device Capabilities Register744.51 Device Control Register754.52 Device Status Register764.53 Link Capabilities Register774.54 Link Control Register784.55 Link Status Register794.56 Serial-Bus Data Register794.57 Serial-Bus Word Address Register794.58 Serial-Bus Slave Address Register804.59 Serial-Bus Control and Status Register814.60 GPIO Control Register824.61 GPIO Data Register834.62 Control and Diagnostic Register 0844.63 Control and Diagnostic Register 1864.64 PHY Control and Diagnostic Register 2874.65 Subsystem Access Register884.66 General Control Register884.67 TI Proprietary Register914.68 TI Proprietary Register914.69 TI Proprietary Register914.70 Arbiter Control Register924.71 Arbiter Request Mask Register934.72 Arbiter Time-Out Status Register944.73 TI Proprietary Register954.74 TI Proprietary Register954.75 TI Proprietary Register955 PCIe Extended Configuration Space965.1 Advanced Error Reporting Capability ID Register965.2 Next Capability Offset/Capability Version Register975.3 Uncorrectable Error Status Register975.4 Uncorrectable Error Mask Register985.5 Uncorrectable Error Severity Register995.6 Correctable Error Status Register1015.7 Correctable Error Mask Register1025.8 Advanced Error Capabilities and Control Register1035.9 Header Log Register1035.10 Secondary Uncorrectable Error Status Register1045.11 Secondary Uncorrectable Error Mask Register1055.12 Secondary Uncorrectable Error Severity1065.13 Secondary Error Capabilities and Control Register1075.14 Secondary Header Log Register1086 Memory-Mapped TI Proprietary Register Space1096.1 Device Control Map ID Register1096.2 Revision ID Register1106.3 GPIO Control Register1106.4 GPIO Data Register1116.5 Serial-Bus Data Register1126.6 Serial-Bus Word Address Register1126.7 Serial-Bus Slave Address Register1126.8 Serial-Bus Control and Status Register1137 1394 OHCI PCI Configuration Space1147.1 Vendor ID Register1157.2 Device ID Register1157.3 Command Register1167.4 Status Register1177.5 Class Code and Revision ID Registers1187.6 Cache Line Size and Latency Timer Registers1187.7 Header Type and BIST Registers1197.8 OHCI Base Address Register1197.9 TI Extension Base Address Register1207.10 CIS Base Address Register1207.11 CIS Pointer Register1217.12 Subsystem Vendor ID and Subsystem ID Registers1217.13 Power Management Capabilities Pointer Register1227.14 Interrupt Line and Interrupt Pin Registers1227.15 Minimum Grant and Minimum Latency Registers1237.16 OHCI Control Register1237.17 Capability ID and Next Item Pointer Registers1247.18 Power Management Capabilities Register1247.19 Power Management Control and Status Register1257.20 Power Management Extension Registers1257.21 PCI Miscellaneous Configuration Register1257.22 Link Enhancement Control Register1287.23 Subsystem Access Register1308 1394 OHCI Memory-Mapped Register Space1318.1 OHCI Version Register1348.2 GUID ROM Register1358.3 Asynchronous Transmit Retries Register1368.4 CSR Data Register1368.5 CSR Compare Register1378.6 CSR Control Register1378.7 Configuration ROM Header Register1388.8 Bus Identification Register1388.9 Bus Options Register1398.10 GUID High Register1408.11 GUID Low Register1408.12 Configuration ROM Mapping Register1418.13 Posted Write Address Low Register1418.14 Posted Write Address High Register1428.15 Vendor ID Register1428.16 Host Controller Control Register1428.17 Self-ID Buffer Pointer Register1458.18 Self-ID Count Register1458.19 Isochronous Receive Channel Mask High Register1468.20 Isochronous Receive Channel Mask Low Register1488.21 Interrupt Event Register1488.22 Interrupt Mask Register1508.23 Isochronous Transmit Interrupt Event Register1528.24 Isochronous Transmit Interrupt Mask Register1538.25 Isochronous Receive Interrupt Event Register1538.26 Isochronous Receive Interrupt Mask Register1548.27 Initial Bandwidth Available Register1548.28 Initial Channels Available High Register1558.29 Initial Channels Available Low Register1558.30 Fairness Control Register1568.31 Link Control Register1578.32 Node Identification Register1588.33 PHY Control Register1598.34 Isochronous Cycle Timer Register1608.35 Asynchronous Request Filter High Register1608.36 Asynchronous Request Filter Low Register1638.37 Physical Request Filter High Register1638.38 Physical Request Filter Low Register1668.39 Physical Upper Bound Register (Optional Register)1668.40 Asynchronous Context Control Register1678.41 Asynchronous Context Command Pointer Register1688.42 Isochronous Transmit Context Control Register1698.43 Isochronous Transmit Context Command Pointer Register1708.44 Isochronous Receive Context Control Register1708.45 Isochronous Receive Context Command Pointer Register1728.46 Isochronous Receive Context Match Register1729 1394 OHCI Memory-Mapped TI Extension Register Space1749.1 Digital Video (DV) and MPEG2 Timestamp Enhancements1749.2 Isochronous Receive Digital Video Enhancements1759.3 Isochronous Receive Digital Video Enhancement Registers1759.4 Link Enhancement Control Registers1769.5 Timestamp Offset Registers17810 Physical Layer (PHY) Section17910.1 PHY Section Register Configuration18010.2 PHY Section Application Information18710.2.1 Power Class Programming18710.2.2 Power-Up Reset18810.2.3 Crystal Oscillator Selection18810.2.4 Bus Reset18911 Electrical Characteristics19011.1 Absolute Maximum Ratings19011.2 Recommended Operating Conditions19011.3 PCIe Differential Transmitter Output Ranges19111.4 PCIe Differential Receiver Input Ranges19311.5 PCIe Differential Reference Clock Input Ranges19411.6 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)19411.7 Electrical Characteristics Over Recommended Operating Conditions (PHY Port Driver)19511.8 Switching Characteristics for PHY Port Driver19511.9 Electrical Characteristics Over Recommended Operating Conditions PHY Port Receiver19611.10 Jitter/Skew Characteristics for 1394a PHY Port Receiver19611.11 Operating, Timing, and Switching Characteristics of XI19611.12 Electrical Characteristics Over Recommended Operating Conditions (1394a Miscellaneous I/O)19612 Glossary196文件大小: 1.2 MB页数: 201Language: English打开用户手册