Texas Instruments IC MCU 16B MSP430F2002IRSAT VQFN-16 TID MSP430F2002IRSAT 数据表
产品代码
MSP430F2002IRSAT
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430F20x3
MSP430F20x2
MSP430F20x1
MSP430F20x2
MSP430F20x1
SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant
program counter, stack pointer, status register, and
constant
generator
respectively.
The
remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
address, and control buses, and can be handled with
all instructions.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
three formats and seven address modes. Each
instruction can operate on word and byte data.
shows examples of the three types of
instruction formats;
shows the address
modes.
Table 5. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 ---> R5
Single operands, destination only
CALL R8
PC -->(TOS), R8--> PC
Relative jump, un/conditional
JNE
Jump-on-equal bit = 0
Table 6. Address Mode Descriptions
ADDRESS MODE
S
(1)
D
(1)
SYNTAX
EXAMPLE
OPERATION
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 --> R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)--> M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) --> M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) --> M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) --> M(Tab+R6)
M(R10) --> R11
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
R10 + 2--> R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 --> M(TONI)
(1)
S = source, D = destination
Copyright © 2005–2012, Texas Instruments Incorporated
11