Microchip Technology DM163025-1 数据表

 2012 Microchip Technology Inc.

DS30684A-page 41

3.7.1

INTRC

The Low-Frequency Internal Oscillator (INTRC) is a
31.25 kHz internal clock source. The INTRC is not
tunable, but is designed to be stable across
temperature and voltage. See 

 for the INTRC accuracy

specifications. 
The output of the INTRC can be a clock source to the
primary clock or the INTOSC clock (see 

INTRC is also the clock source for the Power-up Timer
(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock
Monitor (FSCM).

3.7.2

FREQUENCY SELECT BITS (IRCF)

The HFINTOSC (16 MHz) outputs to a divide circuit
that provides frequencies of 16 MHz to 31.25 kHz.
These divide circuit frequencies, along with the
31.25 kHz   INTRC output, are multiplexed to provide a
single INTOSC clock output (see 

). The

IRCF<2:0> bits of the OSCCON register and the
INTSRC bit of the OSCCON2 register select the output
frequency of the internal oscillators. One of eight
frequencies can be selected via software:
• 16  MHz
• 8  MHz
• 4  MHz
• 2  MHz
• 1 MHz (Default after Reset)
• 500 kHz
• 250 kHz
• 31 kHz (INTRC or HFINTOSC)

3.7.3

INTOSC FREQUENCY DRIFT

The factory calibrates the internal oscillator block outputs
(HFINTOSC) for 16 MHz. However, this frequency may
drift as V

DD

 or temperature changes. It is possible to

automatically tune the HFINTOSC frequency using
USB or secondary oscillator sources using the active
clock tuning module (see 

). The HFINTOSC frequency

may be manually adjusted using the TUN<6:0> bits in
the OSCTUNE register. This has no effect on the INTRC
clock source frequency.
Manually tuning the HFINTOSC source requires
knowing when to make the adjustment, in which
direction it should be made and, in some cases, how
large a change is needed. Three possible compensation
techniques are discussed in the following sections.
However, other techniques may be used.

3.7.3.1

Compensating with the EUSART 

An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high; to
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low; to
compensate, increment OSCTUNE to increase the
clock frequency.

3.7.3.2

Compensating with the Timers

This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast. To adjust for this, decrement
the OSCTUNE register.

3.7.3.3

Compensating with the CCP Module 
in Capture Mode

A CCP module can use free running Timer1 or Timer3
clocked by the internal oscillator block and an external
event with a known period (i.e., AC power frequency).
The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use later.
When the second event causes a capture, the time of the
first event is subtracted from the time of the second
event. Since the period of the external event is known,
the time difference between events can be calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast; to compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow; to compensate, increment the OSCTUNE
register.