Microchip Technology DM183037 数据表
2012 Microchip Technology Inc.
DS30575A-page 93
PIC18F97J94 FAMILY
5.5
Configuration Mismatch
Reset (CM)
Reset (CM)
The Configuration Mismatch (CM) Reset is designed to
detect, and attempt to recover from, random memory
corrupting events. These include Electrostatic
Discharge (ESD) events, which can cause widespread,
single bit changes throughout the device and result in
catastrophic failure.
In PIC18FXXJXX Flash devices, device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by compar-
ing their values to complimentary shadow registers. If a
mismatch is detected between the two sets of registers,
a CM Reset automatically occurs. These events are
captured by the CM bit (RCON<5>) being set to ‘0’.
This bit does not change for any other Reset event. A
CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT Time-out Reset or Stack Event
Reset. As with all hard and power Reset events, the
device’s Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
detect, and attempt to recover from, random memory
corrupting events. These include Electrostatic
Discharge (ESD) events, which can cause widespread,
single bit changes throughout the device and result in
catastrophic failure.
In PIC18FXXJXX Flash devices, device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by compar-
ing their values to complimentary shadow registers. If a
mismatch is detected between the two sets of registers,
a CM Reset automatically occurs. These events are
captured by the CM bit (RCON<5>) being set to ‘0’.
This bit does not change for any other Reset event. A
CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT Time-out Reset or Stack Event
Reset. As with all hard and power Reset events, the
device’s Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
5.6
Brown-out Reset (BOR) Features
The PIC97J94 family has four different types of BOR
circuits:
• Brown-out Reset (BOR)
• V
circuits:
• Brown-out Reset (BOR)
• V
DDCORE
Brown-out Reset (VDDBOR)
• V
BAT
Brown-out Reset (VBATBOR)
• Deep Sleep Brown-out Reset (DSBOR)
All four BOR circuits monitor a voltage and put the
device in a Reset condition while the voltage is in a
specified region. SFRs will reset to the BOR state,
including the Deep Sleep semaphore holding registers,
DSGPR0 and DSGPR1. Upon BOR exit, the device
remains in Reset until the associated trip point voltage
is exceeded. Any I/O pins configured as outputs will be
tri-stated. BOR, VDDBOR and DSBOR exit into Run
mode; VBATBOR remains in V
All four BOR circuits monitor a voltage and put the
device in a Reset condition while the voltage is in a
specified region. SFRs will reset to the BOR state,
including the Deep Sleep semaphore holding registers,
DSGPR0 and DSGPR1. Upon BOR exit, the device
remains in Reset until the associated trip point voltage
is exceeded. Any I/O pins configured as outputs will be
tri-stated. BOR, VDDBOR and DSBOR exit into Run
mode; VBATBOR remains in V
BAT
mode.
These features differ by their power mode, monitored
voltage source, trip points, control and status. Refer to
voltage source, trip points, control and status. Refer to
for the PIC18F97J94 BOR differences.
TABLE 5-1:
BOR FEATURE SUMMARY
)
Feature
Mode
Source
Trip Points
Enable
BOR
Run, Idle, Sleep
V
DDCORE
1.6V (typ)
Always Enabled
VDDBOR
Run, Idle, Sleep
V
DD
V
VDDBOR
BOREN
(CONFIG1H<0>)
VBATBOR
V
BAT
V
BAT
V
VBATBOR
VBTBOR (CONFIG7L<2>)
DSBOR
Deep Sleep
V
DD
V
DSBOR
DSBOREN (CONFIG7L<3>)
Note 1:
for details.