Microchip Technology DM183037 数据表
PIC18F97J94 FAMILY
DS30575A-page 94
2012 Microchip Technology Inc.
5.6.1
BROWN-OUT RESET (BOR)
Brown-out Reset is the legacy PIC18 “J” feature that
monitors the core voltage, V
monitors the core voltage, V
DDCORE
. Since the regulator
on the PIC18F97J94 family is always enabled, this
feature is always active. Its trip point is non-configurable.
A Brown-out Reset will occur as the regulator output
voltage drops below, approximately 1.6V. After proper
operating voltage recovers, the Brown-out Reset condi-
tion is exited and execution begins after the Power-up
Timer has expired. The BOR (RCON<0>) bit is also
cleared. This bit must be set after each Brown-out and
Power-on Reset event to detect subsequent Brown-out
Reset events.
feature is always active. Its trip point is non-configurable.
A Brown-out Reset will occur as the regulator output
voltage drops below, approximately 1.6V. After proper
operating voltage recovers, the Brown-out Reset condi-
tion is exited and execution begins after the Power-up
Timer has expired. The BOR (RCON<0>) bit is also
cleared. This bit must be set after each Brown-out and
Power-on Reset event to detect subsequent Brown-out
Reset events.
5.6.2
V
DD
BOR (V
DDBOR
)
V
DDBOR
is enabled by setting the BOREN
(CONFIG1H<0>) Configuration bit. The low-power
BOR trip level is configurable to either 1.8V or 2.0V,
(typ) depending on the BORV (CONFIG1H<1>) Config-
uration bit setting. When in normal Run mode, Idle or
normal Sleep modes, the BOR circuit that monitors
V
BOR trip level is configurable to either 1.8V or 2.0V,
(typ) depending on the BORV (CONFIG1H<1>) Config-
uration bit setting. When in normal Run mode, Idle or
normal Sleep modes, the BOR circuit that monitors
V
DD
is active and will cause the device to be held in
BOR if V
DD
drops below V
BOR
. Once V
DD
rises back
above V
VDDBOR
, the device will be held in Reset until
the expiration of the Power-up Timer, with period,
T
T
PWRT
. This event is captured by the VDDBOR flag bit
(RCON3<3>).
5.6.3
DETECTING V
DD
BOR
When the BOR module is enabled, the VDDBOR
(RCON3<3>) bit is set on a Brown-out Reset event. This
makes it difficult to determine if a Brown-out Reset event
has occurred just by reading the state of VDDBOR
alone. A more reliable method is to simultaneously
check the state of both VDDPOR and VDDBOR. This
assumes that the VDDPOR bit is reset to ‘1’ in software
immediately after any Power-on Reset event. If
VDDBOR is ‘0’ while VDDPOR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
Legacy PIC18 software can use the respective POR
(RCON<1>) and BOR (RCON<0>) bits. This technique
monitors the regulator output voltage, V
(RCON3<3>) bit is set on a Brown-out Reset event. This
makes it difficult to determine if a Brown-out Reset event
has occurred just by reading the state of VDDBOR
alone. A more reliable method is to simultaneously
check the state of both VDDPOR and VDDBOR. This
assumes that the VDDPOR bit is reset to ‘1’ in software
immediately after any Power-on Reset event. If
VDDBOR is ‘0’ while VDDPOR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
Legacy PIC18 software can use the respective POR
(RCON<1>) and BOR (RCON<0>) bits. This technique
monitors the regulator output voltage, V
DDCORE
. To take
advantage of the configuration features, it is
recommended to use V
recommended to use V
DDBOR
instead of BOR.
5.6.4
V
BAT
BROWN-OUT RESET
(V
BATBOR
)
The V
BAT
BOR can be enabled/disabled using the
VBTBOR bit in the Configuration register
(CONFIG7L<2>). If the VBTBOR enable bit is cleared,
the V
(CONFIG7L<2>). If the VBTBOR enable bit is cleared,
the V
BATBOR
is always disabled and there will be no
indication of a V
BAT
BOR. If the VBTBOR bit is set, the
V
BAT
POR will reset the device when the battery volt-
age drops below V
VBATBOR
. After power is restored to
the V
BAT
pin, the device exits Reset and returns to
V
BAT
mode. The device remains in V
BAT
mode until
power returns to the V
DD
pin. For more information on
using the V
BAT
feature, refer to
5.6.5
DEEP SLEEP BROWN-OUT RESET
(DSBOR)
(DSBOR)
The PIC18F97J94 has its dedicated BOR for Deep
Sleep mode (DSBOR). It is enabled through the
DSBOREN (CONFIG7L<3>) Configuration bit. When
the device enters Deep Sleep mode and receives a
DSBOR event, the device will not wake-up and will
remain in Deep Sleep mode. When a valid wake-up
event occurs and causes the device to exit Deep Sleep
mode, software can determine if a DSBOR event
occurred during Deep Sleep mode by reading the
DSBOR (DSCONL<1>) status bit.
Sleep mode (DSBOR). It is enabled through the
DSBOREN (CONFIG7L<3>) Configuration bit. When
the device enters Deep Sleep mode and receives a
DSBOR event, the device will not wake-up and will
remain in Deep Sleep mode. When a valid wake-up
event occurs and causes the device to exit Deep Sleep
mode, software can determine if a DSBOR event
occurred during Deep Sleep mode by reading the
DSBOR (DSCONL<1>) status bit.
5.7
RESET Instruction
Whenever the RESET instruction is executed, the
device asserts SYSRST. This Reset state does not
re-initialize the clock. The clock source that is in effect
prior to the RESET instruction remains in effect. Config-
uration settings are updated and the SYSRST is
released at the next instruction cycle. A noise filter in
the MCLR Reset path detects and ignores small
pulses. The RI bit (RCON<4>) is cleared when a
RESET instruction is executed. Software must set this
bit to initialize the flag.
device asserts SYSRST. This Reset state does not
re-initialize the clock. The clock source that is in effect
prior to the RESET instruction remains in effect. Config-
uration settings are updated and the SYSRST is
released at the next instruction cycle. A noise filter in
the MCLR Reset path detects and ignores small
pulses. The RI bit (RCON<4>) is cleared when a
RESET instruction is executed. Software must set this
bit to initialize the flag.
5.8
Stack Underflow/Overflow Reset
A Reset can be enabled on stack error conditions by
setting the STVREN (CONFIG1L<5>) Configuration
bit. See
setting the STVREN (CONFIG1L<5>) Configuration
bit. See
section for additional information.
Note:
Brown-out Reset (BOR) has been pro-
vided to support legacy devices that can
disable their internal regulator. The
PIC18F97J94 family’s regulator is always
enabled. Therefore, it’s recommended
that new designs use VDDBOR to detect
Brown-out conditions.
vided to support legacy devices that can
disable their internal regulator. The
PIC18F97J94 family’s regulator is always
enabled. Therefore, it’s recommended
that new designs use VDDBOR to detect
Brown-out conditions.