Texas Instruments Hercules TMS570LS04x/03x LaunchPad Evaluation Kit LAUNCHXL-TMS57004 LAUNCHXL-TMS57004 数据表
产品代码
LAUNCHXL-TMS57004
SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013
Table 5-8. Dynamic Characteristics for the N2HET Input Capture Functionality
PARAMETER
MIN
(1) (2)
MAX
(1) (2)
UNIT
1
Input signal period, PCNT or WCAP for rising edge
(hr)(lr) t
c(VCLK2)
+ 2
2
25
(hr)(lr)t
c(VCLK2)
- 2
ns
to rising edge
2
Input signal period, PCNT or WCAP for falling edge
(hr) (lr) t
c(VCLK2)
+ 2
2
25
(hr)(lr) t
c(VCLK2)
- 2
ns
to falling edge
3
Input signal high phase, PCNT or WCAP for rising
2(hr) t
c(VCLK2)
+ 2
2
25
(hr)(lr) t
c(VCLK2)
- 2
ns
edge to falling edge
4
Input signal low phase, PCNT or WCAP for falling
2(hr) t
c(VCLK2)
+ 2
2
25
(hr)(lr) t
c(VCLK2)
- 2
ns
edge to rising edge
(1)
hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).
(2)
lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR)
5.4.4
N2HET Checking
5.4.4.1
Output Monitoring using Dual Clock Comparator (DCC)
N2HET[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure
the frequency of the pulse-width modulated (PWM) signal on N2HET[31].
the frequency of the pulse-width modulated (PWM) signal on N2HET[31].
N2HET[31] can be configured to be an internal-only channel. That is, the connection to the DCC module is
made directly from the output of the N2HET module (from the input of the output buffer).
made directly from the output of the N2HET module (from the input of the output buffer).
For more information on DCC see
.
5.4.5
Disabling N2HET Outputs
Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET
module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the
N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. Please refer to the
device Technical Reference Manual for more details on the "N2HET Pin Disable" feature.
module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the
N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. Please refer to the
device Technical Reference Manual for more details on the "N2HET Pin Disable" feature.
GIOA[5] and EQEPERR are connected to the "Pin Disable" input for N2HET. In the case of GIOA[5]
connection, this connection is made from the output of the input buffer. In the case of EQEPERR, the
EQEPERR output signal is asserted in the event of a phase error. This signal is inverted and double-
synchronized to VCLK2 for input into the N2HET PIN_nDISABLE port.
connection, this connection is made from the output of the input buffer. In the case of EQEPERR, the
EQEPERR output signal is asserted in the event of a phase error. This signal is inverted and double-
synchronized to VCLK2 for input into the N2HET PIN_nDISABLE port.
The PIN_nDISABLE port input source is selectable between the GIOA[5] and EQEPERR sources. This is
achieved via the PINMMR9[1:0] bits.
achieved via the PINMMR9[1:0] bits.
78
Peripheral Information and Electrical Specifications
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