Freescale Semiconductor DEMO9S08DZ60 Demo Board DEMO9S08DZ60 DEMO9S08DZ60 用户手册
产品代码
DEMO9S08DZ60
D E M O 9 S 0 8 D Z 6 0
D E C E M B E R 2 , 2 0 0 6
11
The RESET switch provides a method to apply an asynchronous RESET to the MCU. The
RESET switch is connected directly to the RESET* input on the MCU. Pressing the RESET
switch applies a low voltage level to the RESET* input. A pull-up bias resistor allows normal
MCU operation. Shunt capacitance ensures an adequate input pulse width.
RESET switch is connected directly to the RESET* input on the MCU. Pressing the RESET
switch applies a low voltage level to the RESET* input. A pull-up bias resistor allows normal
MCU operation. Shunt capacitance ensures an adequate input pulse width.
LOW VOLTAGE RESET
The MC9S08DZ60 utilizes an internal Low Voltage Detect (LVD) circuit. The LVD holds the
MCU in reset until applied voltage reaches an appropriate level. The LVD also protect against
under-voltage conditions. Consult the MC9S08DZ60 reference manual for details LVD
operation.
MCU in reset until applied voltage reaches an appropriate level. The LVD also protect against
under-voltage conditions. Consult the MC9S08DZ60 reference manual for details LVD
operation.
TIMING
The DEMO9S08DZ60 provide 1 internal and 2 external timing sources. The 32 kHz internal
timing source, with ±0.2% resolution, is active out of RESET. An external crystal with ±50ppm
resolution is also provided. A full-size socket allows alternate square-wave clock inputs to be
applied. The target MCU must be configured to select either external timing input source.
Refer to the target MCU documentation for details on configuring external timing inputs.
timing source, with ±0.2% resolution, is active out of RESET. An external crystal with ±50ppm
resolution is also provided. A full-size socket allows alternate square-wave clock inputs to be
applied. The target MCU must be configured to select either external timing input source.
Refer to the target MCU documentation for details on configuring external timing inputs.
The CLK_SEL option header selects the on-board XTAL oscillator, or the optional CLOCK
oscillator socket. The figure below shows settings for CLK_SEL option header.
oscillator socket. The figure below shows settings for CLK_SEL option header.
Figure 4: CLK_SEL Option Header
CLK_SEL
X1
1
2
Select XTAL oscillator X1 output
Y1
3
4
Select Clock oscillator Y1 output (default)
COMMUNICATIONS
The DEMO9S08DZ60 board applies two Serial Communications Interface (SCI) ports. SCI0 is
applied to RS-232 serial communications (COM) on the target board. SCI1 is applied to LIN
communications on the target board. RS-232 communications are supported through a DB9
connector. LIN communications are supported through a pair of 4-pin Molex connectors.
applied to RS-232 serial communications (COM) on the target board. SCI1 is applied to LIN
communications on the target board. RS-232 communications are supported through a DB9
connector. LIN communications are supported through a pair of 4-pin Molex connectors.
RS-232
An RS-232 translator provides RS-232 to TTL/CMOS logic level translation on the COM
connector. The COM connector is a 9-pin Dsub, right-angle connector. A ferrite bead on
shield ground provides conducted immunity protection. Communication signals TXD1 and
RXD1 are routed from the transceiver to the MCU. Hardware flow control signals RTS and
CTS are available on the logic side of the transceiver. These signals are routed to vias located
near the transceiver. RTS has been biased properly to support 2-wire RS-232
communications.
connector. The COM connector is a 9-pin Dsub, right-angle connector. A ferrite bead on
shield ground provides conducted immunity protection. Communication signals TXD1 and
RXD1 are routed from the transceiver to the MCU. Hardware flow control signals RTS and
CTS are available on the logic side of the transceiver. These signals are routed to vias located
near the transceiver. RTS has been biased properly to support 2-wire RS-232
communications.