Freescale Semiconductor Tower System Development Board TWR-56F8400 TWR-56F8400 TWR-56F8400 信息指南

• Clock source from PLL or XOSC/CLKIN
• Implementation of the CAN protocol Version 2.0 A/B
• Standard and extended data frames
• 0-to-8 bytes data length
• Programmable bit rate up to 1 Mbps
• Support for remote frames
• Sixteen Message Buffers, each configurable as receive or transmit, all supporting standard and extended messages
• Individual Rx Mask Registers per Message Buffer
• Internal timer for time-stamping of received and transmitted messages
• Listen-only mode capability
• Programmable loopback mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number, or highest priority
• Global network time, synchronized by a specific message
• Low power modes, with programmable wakeup on bus activity

• Input 2.7 V to 3.6 V (4.0 V absolute maximum rating)
• Provides 1.2 V ± 10% accuracy
• Separate large and small regulators
• Distributed type layout

• Power-on reset (POR) to reset CPU, peripherals, and JTAG/EOnCE controllers (VDD > 2.1 V)
• Brownout reset (VDD < 1.9 V)
• Critical warn low voltage interrupt (LVI2.0)
• Peripheral low voltage interrupt (LVI2.7)

The following table summarizes available development tools.

TWR-56F8400

Cost-effective development board that is part of the Freescale Tower System, a
modular development platform that enables rapid prototyping and re-use through
reconfigurable hardware

TWR-MC-LV3PH

3-Phase Low Voltage Motor Control Module for TWR-56F8400 used to develop DC,
BLDC, and PMSM motor control solutions using various algorithms provided by
Freescale

TWR-MC-STEPPER

Low Voltage Motor Control Module for TWR-56F8400 used to develop stepper motor
control solutions using various algorithms provided by Freescale

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Freescale Semiconductor, Inc.