Freescale Semiconductor Tower System Development Board TWR-56F8400 TWR-56F8400 TWR-56F8400 信息指南

• Detection of loss of lock and loss of reference clock
• Ability to power down

• Two independent 12-bit analog-to-digital converters (ADCs)

• 2 x 8-channel external inputs
• Built-in x1, x2, x4 programmable gain pre-amplifier
• Maximum ADC clock frequency is up to 20 MHz with 50 ns period
• Single conversion time of 8.5 ADC clock cycles (8.5 x 50 ns = 425 ns)
• Additional conversion time of 6 ADC clock cycles (6 x 50 ns = 300 ns)

• Sequential, parallel, and independent scan mode
• First 8 samples have offset, limit and zero-crossing calculation supported
• ADC conversions can be synchronized by any module connected to internal crossbar module, such as PWM and timer

modules and GPIO and comparators

• Support for simultaneous and software triggering conversions
• Support for multi-triggering mode with a programmable number of conversions on each trigger
• Each ADC has ability to scan and store up to 8 conversion results

• Linear successive approximation algorithm with up to 16-bit resolution
• Differential and 16 single-ended external analog inputs
• Maximum ADC clock frequency up to 12.5 MHz
• Output modes: single-ended 16-bit, 12-bit, 10-bit, and 8-bit modes
• Output formatted in 2's complement, 16-bit sign extended for differential modes
• Output in right-justified, unsigned format for single-ended modes
• Single or continuous conversion (automatic return to idle after single conversion)
• Configurable sample time and conversion speed/power
• Conversion complete / hardware average complete flag and interrupt
• Input clock selectable from up to four sources
• Operation in low-power modes for lower-noise operation
• Asynchronous clock source for lower-noise operation with option to output the clock
• Automatic compare with interrupt for less-than, greater-than, or equal-to, within range or out-of-range programmable

value

• Integrated temperature sensor
• Selectable voltage reference: internal, external, or alternate

• 12-bit resolution
• Powerdown mode
• Automatic mode allows the DAC to generate its own output waveforms including square, triangle, and sawtooth

waveforms

• Programmable period, update rate, and range
• Output can be routed to internal comparator, ADC, or optionally off chip

• 2.7 V to 3.3 V operation range
• 64-tap resistor ladder

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Freescale Semiconductor, Inc.