Freescale Semiconductor StarterTRAK USB for Automotive Applications TRK-USB-MPC5604B TRK-USB-MPC5604B TRK-USB-MPC5604B 数据表

Freescale Semiconductor

34

RAM data retention is guaranteed with V

DD_LV

 not below 1.08 V. 

V

SS

SR Digital ground on VSS_HV pins

—

0

0

V

V

DD

1

SR Voltage on VDD_HV pins with respect to 

ground (V

SS

)

—

4.5

5.5

V

Voltage drop

2

3.0

5.5

V

SS_LV

3

SR Voltage on VSS_LV (low voltage digital 

supply) pins with respect to ground (V

SS

)

—

V

SS

0.1 V

SS

+0.1

V

V

DD_BV

4

SR Voltage on VDD_BV pin (regulator supply) 

with respect to ground (V

SS

)

—

4.5

5.5

V

Voltage drop

3.0

5.5

Relative to V

DD

V

DD

0.1 V

DD

+0.1

V

SS_ADC

SR Voltage on VSS_HV_ADC (ADC reference) 

pin with respect to ground (V

SS

—

V

SS

0.1 V

SS

+0.1

V

V

DD_ADC

5

SR Voltage on VDD_HV_ADC pin (ADC 

reference) with respect to ground (V

SS

)

—

4.5

5.5

V

Voltage drop

3.0

5.5

Relative to V

DD

V

DD

0.1 V

DD

+0.1

V

IN

SR Voltage on any GPIO pin with respect to 

ground (V

SS

)

—

V

SS

0.1

—

V

Relative to V

DD

—

V

DD

+0.1

I

INJPAD

SR Injected input current on any pin during 

overload condition

—

5

5

mA

I

INJSUM

SR Absolute sum of all injected input currents 

during overload condition

—

50

50

TV

DD

SR V

DD

 slope to ensure correct power up

6

—

—

0.25

V/µs

T

A C-Grade Part

SR Ambient temperature under bias

f

CPU 



 64 MHz

40

85

°C

T

J C-Grade Part

SR Junction temperature under bias

40

110

T

A V-Grade Part

SR Ambient temperature under bias

40

105

T

J V-Grade Part

SR Junction temperature under bias

40

130

T

A M-Grade Part

SR Ambient temperature under bias

40

125

T

J M-Grade Part

SR Junction temperature under bias

40

150

1

100 nF capacitance needs to be provided between each V

DD

/V

SS

 pair.

2

Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain 
analog electrical characteristics will not be guaranteed to stay within the stated limits.

3

330 nF capacitance needs to be provided between each V

DD_LV

/V

SS_LV

 supply pair.

4

100 nF capacitance needs to be provided between V

DD_BV

 and the nearest V

SS_LV

 (higher value may be needed 

depending on external regulator characteristics).

5

100 nF capacitance needs to be provided between V

DD_ADC

/V

SS_ADC

 pair.

6

Guaranteed by device validation