Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
Background Debug Module (S12XBDMV2)
MC9S12XHY-Family Reference Manual Rev. 1.04
Freescale Semiconductor
213
Figure 5-7. BDM Command Structure
5.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see
. This clock will be referred to as the target clock in
the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
The timing for host-to-target is shown in
and that of target-to-host in
. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since
the host and target are operating from separate clocks, it can take the target system up to one full clock
5. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See
and
for information on how serial clock rate is selected.
Hardware
Hardware
Firmware
Firmware
GO,
48-BC
BC = Bus Clock Cycles
Command
Address
150-BC
Delay
Next
DELAY
8 Bits
AT
~
16 TC/Bit
16 Bits
AT
~
16 TC/Bit
16 Bits
AT
~
16 TC/Bit
Command
Address
Data
Next
Data
Read
Write
Read
Write
TRACE
Command
Next
Command
Data
76-BC
Delay
Next
Command
150-BC
Delay
36-BC
DELAY
Command
Command
Command
Command
Data
Next
Command
TC = Target Clock Cycles