Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
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1.9.3
Freeze Mode
The timer module, pulse width modulator, and analog-to-digital converters provide a software
programmable option to freeze the module status when the background debug module is active. This is
useful when debugging application software. For detailed description of the behavior of the ATD, TIM,
PWM when the background debug module is active consult the corresponding section.
programmable option to freeze the module status when the background debug module is active. This is
useful when debugging application software. For detailed description of the behavior of the ATD, TIM,
PWM when the background debug module is active consult the corresponding section.
1.10
Security
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 5.4.1
Security and Section 18.5 Security
Security and Section 18.5 Security
1.11
Resets and Interrupts
Consult the S12X CPU manual and the S12XINT section for information on exception processing.
NOTE
When referring to the S12XINT section please be aware that the XHY
family neither features an XGATE nor an MPU module.
family neither features an XGATE nor an MPU module.
1.11.1
Resets
Table 1-10. lists all Reset sources and the vector locations. Resets are explained in detail in the
Table 1-10. Reset Sources and Vector Locations
Vector Address
Reset Source
CCR
Mask
Local Enable
$FFFE
Power-On Reset (POR)
None
None
$FFFE
Low Voltage Reset (LVR)
None
None
$FFFE
External pin RESET
None
None
$FFFE
Illegal Address Reset
None
None
$FFFC
Clock monitor reset
None
PLLCTL(CME,SCME)
$FFFA
COP watchdog reset
None
COP rate select