Freescale Semiconductor Reference Design System for MPC8308 MPC8308-RDB MPC8308-RDB 用户手册
产品代码
MPC8308-RDB
System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor
5-73
5.7.3.3
Exiting Core and System Low-Power States
The device can exit low-power state and return to full-on mode for one of the following reasons:
•
The core internal time base unit invokes a request to exit low-power state.
•
The power management controller has detected that the system is not idle and there are outstanding
transactions on the internal bus.
transactions on the internal bus.
The actions taken to exit low-power state depend on the mode and whether the system or only the core are
in this state. The following sections describe the various scenarios.
in this state. The following sections describe the various scenarios.
5.7.3.3.1
Exiting Low-Power States—Core-Only Mode
Exit from doze mode is controlled only by the core itself and does not involve the power management
controller or other blocks in the device.
controller or other blocks in the device.
Nap mode is exited according to the internal time base unit of the core. When the core returns to full-on
state, it signals to the power management controller that it is ready and is immediately acknowledged to
access the DDR2 controller.
state, it signals to the power management controller that it is ready and is immediately acknowledged to
access the DDR2 controller.
5.7.3.3.2
Exiting Low-Power States—Core and System Mode
The power management controller decides to exit low-power state when it detects that the system is not
idle anymore. The device may exit idle state when one of the peripheral interfaces makes a request to
access the internal bus or when the core returns to full-on state, as described above, and makes a request
to access the internal bus. For example, eTSEC wants to read from or write into DDR2 SDRAM memory.
idle anymore. The device may exit idle state when one of the peripheral interfaces makes a request to
access the internal bus or when the core returns to full-on state, as described above, and makes a request
to access the internal bus. For example, eTSEC wants to read from or write into DDR2 SDRAM memory.
If the particular DDR SDRAM memory controller is in low-power state (PMCCR[DLPEN] was set when
entering low-power state), the power management controller initially enables the DDR SDRAM memory
controller and its DLL, allowing it to lock. When locked, DDR SDRAM clocks (MCKn) are enabled and
the memory controller exits self-refresh and returns to auto-refresh mode.
entering low-power state), the power management controller initially enables the DDR SDRAM memory
controller and its DLL, allowing it to lock. When locked, DDR SDRAM clocks (MCKn) are enabled and
the memory controller exits self-refresh and returns to auto-refresh mode.
The power management controller then enables other internal units and interrupts the e300 core. When all
internal units, including the e300 core, are ready, the power management controller enables the device to
return to full-on state, negate the QUIESCE output, and clear PMCCR[SLPEN]. Outstanding requests for
transactions are now granted to execute on the internal bus.
internal units, including the e300 core, are ready, the power management controller enables the device to
return to full-on state, negate the QUIESCE output, and clear PMCCR[SLPEN]. Outstanding requests for
transactions are now granted to execute on the internal bus.