Freescale Semiconductor Reference Design System for MPC8308 MPC8308-RDB MPC8308-RDB 用户手册

Freescale Semiconductor

6-1

 

This chapter describes operation theory of the arbiter in the device. In addition, it describes configuration, 
control, and status registers of the arbiter. 

The arbiter is responsible for providing coherent system bus arbitration. It tracks all address and data 
tenures and provides all the arbitration signals to masters and slaves. In addition, it monitors the bus and 
reports on errors and protocol violations.

The arbiter includes the following features:

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Supports a programmable pipeline depth (from 1 to 4)

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Supports four levels of priority for bus arbitration

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Supports repeat-request mode: number of programmable consecutive transactions from the same 
master (up to eight transactions)

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Supports data streaming operations

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Supports programmable address bus parking mode: disable, park to last bus owner, park to 
software selected master

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Claims address only, reserved and illegal transaction types, report on it and can raise maskable 
interrupt

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Provides timers for address tenure time out and data tenure time out detection and can issue 
maskable interrupt, if any timer expired

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Reports on transfer error and can issue maskable interrupt

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Can issue regular or machine check interrupt for each type of error event (programmable)

The coherent system bus is the central bus of the device. Any data transaction from master to slave in the 
device passes through the coherent system bus. The device coherent system bus supports pipelined 
transactions. It has independent address and data tenures. Pipeline depth determines the number of address 
tenures that can be started before the first data tenure is finished. 

Basic burst size is equal to cache line length of the core, which is 32 bytes. Using repeat request mode 
enables up to eight consecutive bursts to be executed by the same master. The maximum number of