Analog Devices ADP1878 Evaluation Board ADP1878-0.6-EVALZ ADP1878-0.6-EVALZ 数据表

 

Rev. B | Page 23 of 40 

is sensed through the counter action upswing of the output 
(COMP) of the error amplifier.  

The result is a convergence of these two signals (see Figure 78), 
which allows an instantaneous increase in switching frequency 
during the positive load transient event. In summary, a positive 
load step causes V

OUT

 to transient down, which causes COMP to 

transient up and, therefore, shortens the off time. This resulting 
increase in frequency during a positive load transient helps to 
quickly bring V

OUT

 back up in value and within the regulation 

window.  

Similarly, a negative load step causes the off time to lengthen in 
response to V

OUT

 rising. This effectively increases the inductor 

demagnetizing phase, helping to bring V

OUT

 within regulation. 

In this case, the switching frequency decreases, or experiences a 
foldback, to help facilitate output voltage recovery.  

Because the 

 have the ability to respond rapidly 

to sudden changes in load demand, the recovery period in which 
the output voltage settles back to its original steady state operating 
point is much quicker than it would be for a fixed frequency 
equivalent. Therefore, using a pseudo fixed frequency results in 
significantly better load transient performance compared to 
using a fixed frequency. 

 power-good circuitry monitors the 

output voltage via the FB pin. The PGOOD pin is an open-
drain output that can be pulled up by an external resistor to a 
voltage rail that does not necessarily have to be VREG. When 
the internal NMOS switch is in high impedance (off state), this 
means that the PGOOD pin is logic high and the output voltage 
via the FB pin is within the specified regulation window. When 

the internal switch is turned on, PGOOD is internally pulled low 
when the output voltage via the FB pin is outside this regulation 
window. 

The power-good window is defined with a typical upper speci-
fication of +90 mV and a lower specification of −70 mV below 
the FB voltage of 600 mV. When an overvoltage event occurs at the 
output, there is a typical propagation delay of 12 μs prior to the 
deassertion (logic low) of the PGOOD pin. When the output 
voltage reenters the regulation window, there is a propagation 
delay of 12 μs prior to PGOOD reasserting back to a logic high 
state. When the output is outside the regulation window, the 
PGOOD open-drain switch is capable of sinking 1 mA of 
current and providing 140 mV of drop across this switch. The 
user is free to tie the external pull-up resistor (R

RES

) to any 

voltage rail up to 20 V. The following equation provides the 
proper external pull-up resistor value: 

140 mV

1 mA

 

where: 
R

 is the PGOOD external resistor. 

 is a user chosen voltage rail.  

09

44

1

-07

8

09

44

1-

07

9

09

441-08

0