Analog Devices ADP1878 Evaluation Board ADP1878-0.6-EVALZ ADP1878-0.6-EVALZ 数据表
产品代码
ADP1878-0.6-EVALZ
ADP1878/ADP1879
Data
Sheet
Rev. B | Page 26 of 40
EFFICIENCY CONSIDERATION
An important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents of up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents of up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
V
GS (TH)
is the MOSFET voltage applied between the gate
and the source that starts channel conduction.
R
DS (ON)
is the on resistance of the MOSFET during channel
conduction.
Q
G
is the total gate charge.
C
N1
is the input capacitance of the high-side switch.
C
N2
is the input capacitance of the low-side switch.
The following are the losses experienced through the external
component during normal switching operation:
component during normal switching operation:
Channel conduction loss (both of the MOSFETs).
MOSFET driver loss.
MOSFET switching loss.
Body diode conduction loss (low-side MOSFET).
Inductor loss (copper and core loss).
MOSFET driver loss.
MOSFET switching loss.
Body diode conduction loss (low-side MOSFET).
Inductor loss (copper and core loss).
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the high-side MOSFET is directly proportional
to the duty cycle (D) for each switching period, and the power
loss through the low-side MOSFET is directly proportional to
1 − D for each switching period. The selection of MOSFETs is
governed by the maximum dc load current that the converter is
expected to deliver. In particular, the selection of the low-side
MOSFET is dictated by the maximum load current because a
typical high current application employs duty cycles of less than
50%. Therefore, the low-side MOSFET is in the on state for
most of the switching period.
to the power dissipated through MOSFET channel conduction.
Power loss through the high-side MOSFET is directly proportional
to the duty cycle (D) for each switching period, and the power
loss through the low-side MOSFET is directly proportional to
1 − D for each switching period. The selection of MOSFETs is
governed by the maximum dc load current that the converter is
expected to deliver. In particular, the selection of the low-side
MOSFET is dictated by the maximum load current because a
typical high current application employs duty cycles of less than
50%. Therefore, the low-side MOSFET is in the on state for
most of the switching period.
1, 2
1
1
2
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The con-
tributing factors are the dc current flowing through the driver
during operation and the Q
tributing factors are the dc current flowing through the driver
during operation and the Q
GATE
parameter of the external MOSFETs.
P
DR(LOSS)
= [V
DR
× (f
SW
C
upperFET
V
DR
+ I
BIAS
)] + [V
REG
×
(f
SW
C
lowerFET
V
REG
+ I
BIAS
)]
where:
C
C
upperFET
is the input gate capacitance of the high-side MOSFET.
C
lowerFET
is the input gate capacitance of the low-side MOSFET.
I
BIAS
is the dc current flowing into the high- and low-side drivers.
V
DR
is the driver bias voltage (that is, the low input voltage (V
REG
)
minus the rectifier drop (see Figure 83)).
V
V
REG
is the bias voltage.
Figure 83. Internal Rectifier Voltage Drop vs. Switching Frequency
MOSFET Switching Loss
The SW node transitions due to the switching activities of the
high- and low-side MOSFETs. This causes removal and reple-
nishing of charge to and from the gate oxide layer of the MOSFET,
as well as to and from the parasitic capacitance associated with
the gate oxide edge overlap and the drain and source terminals.
The current that enters and exits these charge paths presents
additional loss during these transition times. This can be approxi-
mately quantified by using the following equation, which represents
the time in which charge enters and exits these capacitive regions:
high- and low-side MOSFETs. This causes removal and reple-
nishing of charge to and from the gate oxide layer of the MOSFET,
as well as to and from the parasitic capacitance associated with
the gate oxide edge overlap and the drain and source terminals.
The current that enters and exits these charge paths presents
additional loss during these transition times. This can be approxi-
mately quantified by using the following equation, which represents
the time in which charge enters and exits these capacitive regions:
t
SW-TRANS
= R
GATE
× C
TOTAL
where:
C
C
TOTAL
is the C
GD
+ C
GS
of the external MOSFET.
R
GATE
is the gate input resistance of the external MOSFET.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
is the multiplying factor to be used in the following expression:
-TRANS
2
or
P
SW(LOSS)
= f
SW
× R
GATE
× C
TOTAL
× I
LOAD
× V
IN
× 2
Body Diode Conduction Loss
The
employ anti cross conduction circuitry
that prevents the high- and low-side MOSFETs from conducting
current simultaneously. This overlap control is beneficial, avoiding
large current flow that may lead to irreparable damage to the
external components of the power stage. However, this blanking
period comes with the trade-off of a diode conduction loss
occurring immediately after the MOSFETs change states and
continuing well into idle mode.
current simultaneously. This overlap control is beneficial, avoiding
large current flow that may lead to irreparable damage to the
external components of the power stage. However, this blanking
period comes with the trade-off of a diode conduction loss
occurring immediately after the MOSFETs change states and
continuing well into idle mode.
800
720
640
560
480
400
320
240
160
80
300
1000
900
800
700
600
500
400
RE
CT
IF
IE
R V
O
L
T
AG
E
DRO
P
(
m
V
)
SWITCHING FREQUENCY (kHz)
+125°C
+25°C
–40°C
+25°C
–40°C
V
REG
= 2.7V
V
REG
= 3.6V
V
REG
= 5.5V
094
41-
083