Linear Technology LTC2188: 16-bit 20Msps Dual ADC, DDR LVDS Outputs, 5-140MHz, req DC890, LVDS_XFMR and DC1075 DC1620A-S DC1620A-S 数据表

产品代码

DC1620A-S

LTC2188

2188f

pin FuncTions

SENSE (Pin 63): Reference Programming Pin. Connecting

SENSE to V

selects the internal reference and a ±1V input

range. Connecting SENSE to ground selects the internal

reference and a ±0.5V input range. An external reference

between 0.625V and 1.3V applied to SENSE selects an

input range of ±0.8 • V

SENSE

Ground (Exposed Pad Pin 65): The exposed pad must be

soldered to the PCB ground.

FULL-RATE CMOS OUTPUT MODE

All Pins Below Have CMOS Output Levels

(OGND to OV

)

D2_0 to D2_15 (Pins 23, 24, 25, 26, 27, 28, 29, 30, 31,

32, 33, 34, 35, 36, 37, 38): Channel 2 Digital Outputs.

D2_15 is the MSB.
CLKOUT

–

(Pin 39): Inverted version of CLKOUT

CLKOUT

(Pin 40): Data Output Clock. The digital outputs

normally transition at the same time as the falling edge

of CLKOUT

. The phase of CLKOUT

can also be delayed

relative to the digital outputs by programming the mode

control registers.
D1_0 to D1_15 (Pins 43, 44, 45, 46, 47, 48, 49, 50, 51,

52, 53, 54, 55, 56, 57, 58): Channel 1 Digital Outputs.

D1_15 is the MSB.
OF2 (Pin 59): Channel 2 Over/Under Flow Digital Output.

OF2 is high when an overflow or underflow has occurred.
OF1 (Pin 60): Channel 1 Over/Under Flow Digital Output.

OF1 is high when an overflow or underflow has occurred.

DOUBLE DATA RATE CMOS OUTPUT MODE

All Pins Below Have CMOS Output Levels

(OGND to OV

)

D2_0_1 to D2_14_15 (Pins 24, 26, 28, 30, 32, 34, 36,

38): Channel 2 Double Data Rate Digital Outputs. Two data

bits are multiplexed onto each output pin. The even data

bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when

CLKOUT

is low. The odd data bits (D1, D3, D5, D7, D9,

D11, D13, D15) appear when CLKOUT

is high.

DNC (Pins 23, 25, 27, 29, 31, 33, 35, 37, 43, 45, 47,

49, 51, 53, 55, 57, 59): Do not connect these pins.
CLKOUT

–

(Pin 39): Inverted version of CLKOUT

CLKOUT

(Pin 40): Data Output Clock. The digital outputs

normally transition at the same time as the falling and ris-

ing edges of CLKOUT

. The phase of CLKOUT

can also

be delayed relative to the digital outputs by programming

the mode control registers.
D1_0_1 to D1_14_15 (Pins 44, 46, 48, 50, 52, 54, 56,

58): Channel 1 Double Data Rate Digital Outputs. Two data

bits are multiplexed onto each output pin. The even data

bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when

CLKOUT

is low. The odd data bits (D1, D3, D5, D7, D9,

D11, D13, D15) appear when CLKOUT

is high.

OF2_1 (Pin 60): Over/Under Flow Digital Output. OF2_1

is high when an overflow or underflow has occurred. The

over/under flow for both channels are multiplexed onto

this pin. Channel 2 appears when CLKOUT

is low, and

Channel 1 appears when CLKOUT

is high.