Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
365
32072H–AVR32–10/2012
AT32UC3A3
19.12.11 Interrupt Raw Status Registers
Name:
RawTfr, RawBlock, RawSrcTran, RawDstTran, RawErr
Access Type: Read-only
Offset:
0x2C0, 0x2C8, 0x2D0, 0x2D8, 0x2E0
Reset Value:
0x00000000
• RAW[3:0]Raw interrupt for each channel
Interrupt events are stored in these Raw Interrupt Status Registers before masking: RawTfr, RawBlock, RawSrcTran,
RawDstTran, RawErr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr[2] is Chan-
nel 2’s raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in
the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers.
RawDstTran, RawErr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr[2] is Chan-
nel 2’s raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in
the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
-
-
-
RAW3
RAW2
RAW1
RAW0