Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
367
32072H–AVR32–10/2012
AT32UC3A3
19.12.13 Interrupt Mask Registers
Name:
MaskTfr, MaskBlock, MaskSrcTran, MaskDstTran, MaskErr
Access Type: Read/Write
Offset:
0x310, 0x318, 0x320, 0x328, 0x330
Reset Value:
0x00000000
The contents of the Raw Status Registers are masked with the contents of the Mask Registers: MaskTfr, MaskBlock, Mask-
SrcTran, MaskDstTran, MaskErr. Each Interrupt Mask register has a bit allocated per channel, for example, MaskTfr[2] is
the mask bit for Channel 2’s transfer complete interrupt.
SrcTran, MaskDstTran, MaskErr. Each Interrupt Mask register has a bit allocated per channel, for example, MaskTfr[2] is
the mask bit for Channel 2’s transfer complete interrupt.
A channel’s INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted
on the same System Bus write transfer. This allows software to set a mask bit without performing a read-modified write
operation.
on the same System Bus write transfer. This allows software to set a mask bit without performing a read-modified write
operation.
For example, writing hex 01x1 to the MaskTfr register writes a 1 into MaskTfr[0], while MaskTfr[7:1] remains unchanged.
Writing hex 00xx leaves MaskTfr[7:0] unchanged.
Writing hex 00xx leaves MaskTfr[7:0] unchanged.
Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMACA to set the appropri-
ate bit in the Status Registers.
ate bit in the Status Registers.
• INT_M_WE[11:8]: Interrupt Mask Write Enable
0 = Write disabled
1 = Write enabled
• INT_MASK[3:0]: Interrupt Mask
0= Masked
1 = Unmasked
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
-
INT_M_WE3
INT_M_WE2
INT_M_WE1
INT_M_WE0
7
6
5
4
3
2
1
0
-
-
-
-
INT_MASK3
INT_MASK2
INT_MASK1
INT_MASK0