Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

RFMR

Read/Write

0x14

0x00000000 

The four MSB of the FSLEN field.

Determines which edge on Frame Sync will generate the SR.RXSYN interrupt.

This field defines the length of the Receive Frame Sync signal and the number of bits sampled and stored in the RSHR register. 

When this mode is selected by the RCMR.START field, it also determines the length of the sampled data to be compared to the 

Compare 0 or Compare 1 register.

Note: The four most significant bits for this field are located in the FSLENHI field.

The pulse length is equal to ({FSLENHI,FSLEN} + 1) receive clock periods. Thus, if {FSLENHI,FSLEN} is zero, the Receive 

Frame Sync signal is generated during one receive clock period.

31

30

29

28

27

26

25

24

FSLENHI

-

-

-

FSEDGE

23

22

21

20

19

18

17

16

-

FSOS

FSLEN

15

14

13

12

11

10

9

8

-

-

-

-

DATNB

7

6

5

4

3

2

1

0

MSBF

-

LOOP

DATLEN

0

Positive edge detection

1

Negative edge detection

0

None

Input-only

1

Negative Pulse

Output

2

Positive Pulse

Output

3

Driven Low during data transfer

Output

4

Driven High during data transfer

Output

5

Toggling at each start of data transfer

Output

Others

Reserved

Undefined