Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
531
32072H–AVR32–10/2012
AT32UC3A3
24.9.5
Transmit Clock Mode Register
Name:
TCMR
Access Type:
Read/Write
Offset:
0x18
Reset value:
0x00000000
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected transmit clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) transmit clock periods.
• STTDLY: Transmit Start Delay
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission.
When the transmitter is programmed to start synchronously with the receiver, the delay is also applied.
Note: STTDLY must be written carefully, in relation to Transmit Sync Data transmission.
• START: Transmit Start Selection
31
30
29
28
27
26
25
24
PERIOD
23
22
21
20
19
18
17
16
STTDLY
15
14
13
12
11
10
9
8
-
-
-
-
START
7
6
5
4
3
2
1
0
CKG
CKI
CKO
CKS
START
Transmit Start
0
Continuous, as soon as a word is written to the THR Register (if Transmit is enabled), and
immediately after the end of transfer of the previous data.
immediately after the end of transfer of the previous data.
1
Receive start
2
Detection of a low level on TX_FRAME_SYNC signal
3
Detection of a high level on TX_FRAME_SYNC signal
4
Detection of a falling edge on TX_FRAME_SYNC signal
5
Detection of a rising edge on TX_FRAME_SYNC signal
6
Detection of any level change on TX_FRAME_SYNC signal
7
Detection of any edge on TX_FRAME_SYNC signal
Others
Reserved