Nxp Semiconductors OM11043 数据表

LPC1769_68_67_66_65_64_63

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© NXP Semiconductors N.V. 2014. All rights reserved.

 

Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on 
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt 
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains 
a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see 
description in 

). The wake-up timer ensures that reset remains asserted 

until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks 
have passed, and the flash controller has completed its initialization. Once reset is 
de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD 
threshold, the RSTOUT pin goes HIGH.

When the internal Reset is removed, the processor begins executing at address 0, which 
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor 
and peripheral registers have been initialized to predetermined values.

REAL-TIME CLOCK

BACKUP REGISTERS

REGULATOR

32 kHz

OSCILLATOR

RTC POWER DOMAIN

MAIN POWER DOMAIN

RTCX1

VBAT

V

DD(REG)(3V3)

RTCX2

V

DD(3V3)

V

SS

to memories,
peripherals, 
oscillators,
PLLs

to core

to I/O pads

ADC

DAC

ADC POWER DOMAIN

V

DDA

VREFP

VREFN

V

SSA

ULTRA LOW-POWER

REGULATOR

POWER

SELECTOR