Nxp Semiconductors OM11043 数据表

LPC1769_68_67_66_65_64_63

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© NXP Semiconductors N.V. 2014. All rights reserved.

The LPC17xx include 2-stage monitoring of the voltage on the V

DD(REG)(3V3)

 pins. If this 

voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt 
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the 
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading 
a dedicated status register.

The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when 
the voltage on the V

DD(REG)(3V3)

 pins falls below 1.85 V. This reset prevents alteration of 

the flash as operation of the various elements of the chip would otherwise become 
unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at 
which point the power-on reset circuitry maintains the overall reset.

Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this 
hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event 
loop to sense the condition.

This feature of the LPC17xx allows user to enable different levels of security in the system 
so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When 
needed, CRP is invoked by programming a specific pattern into a dedicated flash location. 
IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding 
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is 
required and flash field updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full flash erase and update 
using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the 
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. 
It is up to the user’s application to provide (if needed) flash update mechanism using IAP 
calls or call reinvoke ISP command to enable flash update via UART0.

 

The APB peripherals are split into two separate APB buses in order to distribute the bus 
bandwidth and thereby reducing stalls caused by contention between the CPU and the 
GPDMA controller.

If level three Code Read Protection (CRP3) is selected, no future factory testing can be 
performed on the device.