Nxp Semiconductors OM11043 数据表

LPC1769_68_67_66_65_64_63

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© NXP Semiconductors N.V. 2014. All rights reserved.

 

[1]

See the I

2

C-bus specification UM10204 for details.

[2]

Parameters are valid over operating temperature range unless otherwise specified. 

[3]

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the 
V

IH

(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[4]

C

b

 = total capacitance of one bus line in pF. 

[5]

The maximum t

f

 for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA 

output stage t

f

 is specified at 250 ns. This allows series protection resistors to be connected in between the 

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t

f

.

[6]

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors 
are used, designers should allow for this when considering bus timing.

[7]

tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission 
and the acknowledge.

[8]

The maximum t

HD;DAT

 could be 3.45 

s and 0.9 s for Standard-mode and Fast-mode but must be less than 

the maximum of t

VD;DAT

 or t

VD;ACK

 by a transition time (see the I

2

C-bus specification UM10204). This 

maximum must only be met if the device does not stretch the LOW period (t

LOW

) of the SCL signal. If the 

clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9]

tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in 
transmission and the acknowledge.

[10] A Fast-mode I

2

C-bus device can be used in a Standard-mode I

2

C-bus system but the requirement t

SU;DAT

 = 

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period 
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next 
data bit to the SDA line t

r(max)

 + t

SU;DAT

 = 1000 + 250 = 1250 ns (according to the Standard-mode I

2

C-bus 

specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.







f

SCL

SCL clock 
frequency

Standard-mode

0

100

kHz

Fast-mode

0

400

kHz

Fast-mode Plus

0

1

MHz

t

f

fall time

of both SDA and 
SCL signals

Standard-mode

-

300

ns

Fast-mode

20 + 0.1 

 C

b

300

ns

Fast-mode Plus

-

120

ns

t

LOW

LOW period of 
the SCL clock

Standard-mode

4.7

-

s

Fast-mode

1.3

-

s

Fast-mode Plus

0.5

-

s

t

HIGH

HIGH period of 
the SCL clock

Standard-mode

4.0

-

s

Fast-mode

0.6

-

s

Fast-mode Plus

0.26

-

s

t

HD;DAT

data hold time

Standard-mode

0

-

s

Fast-mode

0

-

s

Fast-mode Plus

0

-

s

t

SU;DAT

data set-up 
time 

 

Standard-mode

250

-

ns

Fast-mode

100

-

ns

Fast-mode Plus

50

-

ns