Nxp Semiconductors OM11043 数据表
LPC1769_68_67_66_65_64_63
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Product data sheet
Rev. 9.5 — 24 June 2014
59 of 89
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
12.6 I
2
S-bus interface
Remark: The I
2
S-bus interface is available on parts LPC1769/68/67/66/65/63. See
[1]
CCLK = 20 MHz; peripheral clock to the I
2
S-bus interface PCLK =
CCLK
⁄
4
; I
2
S clock cycle time T
cy(clk)
= 1600 ns, corresponds to the SCK
signal in the I
2
S-bus specification.
Fig 18. I
2
C-bus pins clock timing
002aaf425
t
f
70 %
30 %
SDA
t
f
70 %
30 %
S
70 %
30 %
70 %
30 %
30 %
t
HD;DAT
SCL
1 / f
SCL
70 %
30 %
70 %
30 %
t
VD;DAT
t
HIGH
t
LOW
t
SU;DAT
Table 15.
Dynamic characteristics: I
2
S-bus interface pins
T
amb
=
40
C to +85
C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
common to input and output
t
r
rise time
-
-
35
ns
t
f
fall time
-
-
35
ns
t
WH
pulse width HIGH
on pins I2STX_CLK and
I2SRX_CLK
I2SRX_CLK
0.495
T
cy(clk)
-
-
-
t
WL
pulse width LOW
on pins I2STX_CLK and
I2SRX_CLK
I2SRX_CLK
-
-
0.505
T
cy(clk)
ns
output
t
v(Q)
data output valid time
on pin I2STX_SDA
-
-
30
ns
on pin I2STX_WS
-
-
30
ns
input
t
su(D)
data input set-up time
on pin I2SRX_SDA
3.5
-
-
ns
t
h(D)
data input hold time
on pin I2SRX_SDA
4.0
-
-
ns