Nxp Semiconductors OM11043 数据表

LPC1769_68_67_66_65_64_63

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2014. All rights reserved.

 

(1) Not available on all parts. See 

.

SRAM 32/64 kB

ARM

CORTEX-M3

TEST/DEBUG

INTERFACE

EMULA

TION

TRA

CE MODULE

FLASH

ACCELERATOR

FLASH

512/256/128 kB

DMA

CONTROLLER

ETHERNET

CONTROLLER

WITH DMA

(1)

USB HOST/

DEVICE/OTG

CONTROLLER

WITH DMA

(1)

I-code
bus

D-code
bus

system
bus

AHB TO

APB

BRIDGE 0

HIGH-SPEED

GPIO

AHB TO

APB

BRIDGE 1

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM 

FUNCTIONS

XTAL1

XTAL2

RESET

clocks and 

controls

JTAG

interface

debug

port

USB PHY

SSP0

UART2/3

I2S

(1)

I2C2

RI TIMER

TIMER2/3

EXTERNAL INTERRUPTS

SYSTEM CONTROL

MOTOR CONTROL PWM

QUADRATURE ENCODER

SSP1

UART0/1

CAN1/2

(1)

I2C0/1

SPI0

TIMER 0/1

WDT

PWM1

12-bit ADC

PIN CONNECT

GPIO INTERRUPT CONTROL

RTC

BACKUP REGISTERS

32 kHz

OSCILLATOR

APB slave group 1

APB slave group 0

DAC

(1)

RTC POWER DOMAIN

master

master

master

slave

slave

slave

slave

slave

ROM

slave

MULTILAYER AHB MATRIX

P0 to

P4

SDA2

SCL2

SCK0
SSEL0
MISO0
MOSI0

SCK1

SSEL1
MISO1
MOSI1

RXD2/3
TXD2/3

PHA, PHB

INDEX

EINT[3:0]

AOUT

MCOA[2:0]
MCOB[2:0]
MCI[2:0]
MCABORT

4 

× 

MAT2

2 

× 

MAT3

2 

× 

CAP2

2 

× 

CAP3

3 

×

 I2SRX

3 

× 

I2STX

TX_MCLK
RX_MCLK

RTCX1

RTCX2

VBAT

PWM1[7:0]

2 

×

 MAT0/1

2 

×

 CAP0/1

RD1/2

TD1/2

SDA0/1

SCL0/1

AD0[7:0]

SCK/SSEL

MOSI/MISO

8 

×

 UART1

RXD0/TXD0

P0, P2

PCAP1[1:0]

RMII pins

USB pins

CLKOUT

MPU

= connected to DMA