Nxp Semiconductors OM11043 数据表

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页码 89
LPC1769_68_67_66_65_64_63
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 9.5 — 24 June 2014 
8 of 89
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
 
 
Fig 4.
Pin configuration WLCSP100 package
Transparent top view
1
A
B
C
D
E
F
G
H
J
K
2
3
4
5
6
7
8
9
10
LPC1768UK
bump A1
index area
aaa-009522
Table 4.
Pin allocation table TFBGA100
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
Row A
1
TDO/SWO
2
P0[3]/RXD0/AD0[6]
3
V
DD(3V3)
4
P1[4]/ENET_TX_EN 
5
P1[10]/ENET_RXD1
6
P1[16]/ENET_MDC
7
V
DD(REG)(3V3)
8
P0[4]/I2SRX_CLK/
RD2/CAP2[0]
9
P0[7]/I2STX_CLK/
SCK1/MAT2[1]
10
P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
11
-
12
-
Row B
1
TMS/SWDIO
2
RTCK
3
V
SS
4
P1[1]/ENET_TXD1
5
P1[9]/ENET_RXD0
6
P1[17]/
ENET_MDIO
7
V
SS
8
P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
9
P2[0]/PWM1[1]/TXD1
10
P2[1]/PWM1[2]/RXD1
11
-
12
-
Row C
1
TCK/SWDCLK
2
TRST
3
TDI
4
P0[2]/TXD0/AD0[7]
5
P1[8]/ENET_CRS
6
P1[15]/
ENET_REF_CLK
7
P4[28]/RX_MCLK/
MAT2[0]/TXD3
8
P0[8]/I2STX_WS/
MISO1/MAT2[2]
9
V
SS
10
V
DD(3V3)
11
-
12
-
Row D
1
P0[24]/AD0[1]/
I2SRX_WS/CAP3[1]
2
P0[25]/AD0[2]/
I2SRX_SDA/TXD3
3
P0[26]/AD0[3]/
AOUT/RXD3
4
n.c.
5
P1[0]/ENET_TXD0
6
P1[14]/ENET_RX_ER
7
P0[5]/I2SRX_WS/
TD2/CAP2[1]
8
P2[2]/PWM1[3]/
CTS1/TRACEDATA[3]
9
P2[4]/PWM1[5]/
DSR1/TRACEDATA[1]
10
P2[5]/PWM1[6]/
DTR1/TRACEDATA[0]
11
-
12
-
Row E
1
V
SSA
2
V
DDA
3
VREFP
4
n.c.
5
P0[23]/AD0[0]/
I2SRX_CLK/CAP3[0]
6
P4[29]/TX_MCLK/
MAT2[1]/RXD3
7
P2[3]/PWM1[4]/
DCD1/TRACEDATA[2]
8
P2[6]/PCAP1[0]/
RI1/TRACECLK