Intel D2500 DF8064101055400 数据表
产品代码
DF8064101055400
28
Datasheet - Volume 1 of 2
2.9
DDI Port1
2.10
JTAG/ITP Signals
Table 2-16.DDI Port 1
Signal Name
Description
Direction
Type
DDI1_TXP[3:0],
DDI1_TXN[3:0]
DDI1_TXN[3:0]
PORT1: Capable of HDMI/DVI/DP/eDP
HDMI/DVI:
TX[0]: TMDSB_DATA2
TX[1]: TMDSB_DATA1
TX[2]: TMDSB_DATA0
TX[3]: TMDSB_BLK
eDP/DP:
TX[0]: DPort Lane 0 (BLUE, HSYNC, VSYNC)
TX[1]: DPort Lane 1 (GRN, CTL0, CTL1)
TX[2]: DPort Lane 2 (Red, CTL2, CTL3)
TX[3]: DPort Lane 3
HDMI/DVI:
TX[0]: TMDSB_DATA2
TX[1]: TMDSB_DATA1
TX[2]: TMDSB_DATA0
TX[3]: TMDSB_BLK
eDP/DP:
TX[0]: DPort Lane 0 (BLUE, HSYNC, VSYNC)
TX[1]: DPort Lane 1 (GRN, CTL0, CTL1)
TX[2]: DPort Lane 2 (Red, CTL2, CTL3)
TX[3]: DPort Lane 3
O
Diff
DDI1_AUXP,
DDI1_AUXN
DDI1_AUXN
DP: Display port aux
HDMI/DVI: Unused
HDMI/DVI: Unused
I/O
Diff
DDI1_HPD
DDI1 Hot Plug Detect
I
OD
DDI1_DDC_SDA,
DDI1_DDC_SCL
DDI1_DDC_SCL
I2C Control Clock and Data.
HDMI and DP dual mode
DDI1_DDC_SDA sampled as a pin-strap for
HDMI and DP dual mode
DDI1_DDC_SDA sampled as a pin-strap for
HDMI/DVI/DP port presence detect.
I/O
OD
DPL_REFSSCCLKP,
DPL_REFSSCCLKN
SSC Display PLL Reference:
100 MHz SSC (Spread Spectrum Clocking)
100 MHz SSC (Spread Spectrum Clocking)
I
Diff
Table 2-17.JTAG/ITP Signals
Signal
Name
Description Direction
Type
TCLK
TCLK (Test Clock) provides the clock input for the
processor Test Bus (also known as the Test Access Port).
I
CMOS
TDI
TDI (Test Data In) transfers serial test data into the
processor. TDI provides the serial input needed for JTAG
specification support.
I
CMOS
TDO
TDO (Test Data Out) transfers serial test data out of the
processor. TDO provides the serial output needed for
JTAG specification support.
O
OD
TMS
TMS (Test Mode Select) is a JTAG specification support
signal used by debug tools.
I
CMOS
TRST#
TRST_B (Test Reset) resets the Test Access Port (TAP)
logic.
I
CMOS