Renesas Stereo System SH7709S 用户手册
Rev. 5.00, 09/03, page 186 of 760
Bit 4—Module Stop 7 (MSTP7): Specifies halting of the clock supply to the DMAC (an on-chip
peripheral module). When the MSTP7 bit is set to 1, the supply of the clock to the DMAC is
halted.
peripheral module). When the MSTP7 bit is set to 1, the supply of the clock to the DMAC is
halted.
Bit 4: MSTP7
Description
0
DMAC runs
(Initial value)
1
Clock supply to DMAC halted
Bit 3—Module Stop 6 (MSTP6): Specifies halting of the clock supply to the DAC (an on-chip
peripheral module). When the MSTP6 bit is set to 1, the supply of the clock to the DAC is halted.
peripheral module). When the MSTP6 bit is set to 1, the supply of the clock to the DAC is halted.
Bit 3: MSTP6
Description
0
DAC runs
(Initial value)
1
Clock supply to DAC halted
Bit 2—Module Stop 5 (MSTP5): Specifies halting of the clock supply to the ADC (an on-chip
peripheral module). When the MSTP5 bit is set to 1, the supply of the clock to the ADC is halted
and all registers are initialized.
peripheral module). When the MSTP5 bit is set to 1, the supply of the clock to the ADC is halted
and all registers are initialized.
Bit 2: MSTP5
Description
0
ADC runs
(Initial value)
1
Clock supply to ADC halted and all registers initialized
Bit 1—Module Stop 4 (MSTP4): Specifies halting of the clock supply to the SCI2 (SCIF) serial
communication interface with FIFO (an on-chip peripheral module). When the MSTP1 bit is set to
1, the supply of the clock to SCI2 (SCIF) is halted.
communication interface with FIFO (an on-chip peripheral module). When the MSTP1 bit is set to
1, the supply of the clock to SCI2 (SCIF) is halted.
Bit 1: MSTP4
Description
0
SCI2 (SCIF) runs
(Initial value)
1
Clock supply to SCI2 (SCIF) halted
Bit 0—Module Stop 3 (MSTP3): Specifies halting of the clock supply to the SCI1 (IrDA)
Infrared Data Association interface with FIFO (an on-chip peripheral module). When the MSTP3
bit is set to 1, the supply of the clock to SCI1 (IrDA) is halted.
Infrared Data Association interface with FIFO (an on-chip peripheral module). When the MSTP3
bit is set to 1, the supply of the clock to SCI1 (IrDA) is halted.
Bit 0: MSTP3
Description
0
SCI1(IrDA) runs
(Initial value)
1
Clock supply to SCI1(IrDA) halted