FIC A360 用户手册
Troubleshooting and Repair
Table 6-3 (d)
BIOS Beep Codes
Beep
Code
Diagnostic
Code
Description Test
Performed
4-2-3
36h
Gate A20 failure.
To test extended memory, the processor
must be placed in protected mode and
the A20 line must be enabled. For the
memory tests, the BIOS generally uses
the keyboard controller to enable A20. If
the A20 line is not properly set during the
memory test, an error message is
displayed on the screen and the memory
test are suspended. The system does
not halt.
must be placed in protected mode and
the A20 line must be enabled. For the
memory tests, the BIOS generally uses
the keyboard controller to enable A20. If
the A20 line is not properly set during the
memory test, an error message is
displayed on the screen and the memory
test are suspended. The system does
not halt.
4-2-4 37h
Unexpected interrupt in
protected mode.
protected mode.
During the memory tests, the processor
is placed in protected mode. All
interrupts in the interrupt descriptor table
are initialized to point to special handler
that displays a message on the screen.
All hardware interrupt are disabled. The
system does not halt when an
unexpected interrupt occurs.
is placed in protected mode. All
interrupts in the interrupt descriptor table
are initialized to point to special handler
that displays a message on the screen.
All hardware interrupt are disabled. The
system does not halt when an
unexpected interrupt occurs.
4-3-1 38h
RAM test of memory above
64K in progress or failure.
64K in progress or failure.
The memory above the first 64K is tested
with a rolling ones test and a pattern test.
All success and failure messages are
displayed on the screen and POST will
continue.
with a rolling ones test and a pattern test.
All success and failure messages are
displayed on the screen and POST will
continue.
4-3-2 3Ah
Programmable interval timer
channel 2 test in progress or
failure.
channel 2 test in progress or
failure.
Over a period of time, the current count
values in timer 2 are read and
accumulated by ORing them into the
values read so far. It is expected that
during the time period, all bits will be set.
If an error is detected, an error message
will be displayed on the screen and
POST will continue.
values in timer 2 are read and
accumulated by ORing them into the
values read so far. It is expected that
during the time period, all bits will be set.
If an error is detected, an error message
will be displayed on the screen and
POST will continue.
4-3-4 3Bh
Real-time clock test in
progress or failure.
progress or failure.
Over a period of time, the Update-In-
Progress bit of Status Register A of the
real-time clock is read and tested. The bit
should toggle from 0 to 1 within the time
period.
Progress bit of Status Register A of the
real-time clock is read and tested. The bit
should toggle from 0 to 1 within the time
period.
4-4-1 3Ch
Serial port test in progress or
failure.
failure.
Pattern test of one or more of the
installed serial ports. If a failure is
detected, an error message will be
displayed and POST will continue.
installed serial ports. If a failure is
detected, an error message will be
displayed and POST will continue.
4-4-2 3Dh
Parallel port test in progress
or failure.
or failure.
Rolling ones test is done to one or more
of the installed parallel ports. If a failure
is detected, an error message will be
displayed and POST will continue.
of the installed parallel ports. If a failure
is detected, an error message will be
displayed and POST will continue.
4-4-3 3Eh
Math coprocessor test in
progress or failure.
progress or failure.
An integer load and store is performed
with the math coprocessor. If the values
do not match, an error message will be
displayed and POST will continue.
with the math coprocessor. If the values
do not match, an error message will be
displayed and POST will continue.
6-8
FIC A360 Service Manual