Acorn Products Z80 SECOND PROCESSSOR 409 用户手册

memory control signals go active. The Refresh address is incremented 

by the CPU after each time.

Once  the  MREQ  signal  goes  active,  the  "D"  latch  1C18B  produces  CPOP 

and hence RAS as normal. The CAS is not required for a Refresh cycle, 

and is not enabled since none of the conditions listed in section 5.7.

1b are true (AND gate IC20C).

When  the  shadow  ROM  is  being  read,  the  CAS  signal  to  the  DRAMS  is 

disabled,  but  the  row-address  latch  signal,  RAS,  sti11  occurs.  This 

has the effect of a refresh cycle to the DRAMS.

5.9 Desynchronising Logic

To  prevent  ambiguous  events,  i.e.  a  register  status  change  during  a 

status  read,  this  circuit  produces  a  "WA1T"  signal  to  the  Z80 

processor when the PCS and HCS signals occur simultaneously.

When this happens, a low signal from IC29B pin 6 appears at IC30A pin 

2.  Q  on  IC30A  goes  high  and,  via  IC29A,  maintains  a  logic  1  signal 

upon pin 12 of IC30B, thus, by the end of one clock cycle a high is 

sent from pin 9 of IC30B to disable PCS. Simultaneously, a WAIT signal 

is generated for the second processor via IC19A&B.

As soon as  HCS (TP6) is removed, the next rising clock edge removes 

the WAIT signal from the Z80 and, as PCS is still low, a 

low signal is sent 

through IC30B to the 

Tube. This is then 

maintained by the 

low signal upon pin 

4 of IC30A until the 

PCS is complete.

Thus, if PCS (TP5) 

is already running, 

it will continue 

despite an HCS, but 

if HCS began first 

then PCS is 

prevented from 

acting.

*At no time is PCS 

affected, as it 

would not be 

possible to 'stop' 

the BBC processor.