Acorn Products Z80 SECOND PROCESSSOR 409 用户手册
6.3 Circuit Checks
6.3.1 Clock
Using an oscilloscope, check that a 12MHz signal is being generated
at pin 13 of IC22D. If not, check the crystal X1, resistor values and
operation of inverters IC24D/E. Trace the signal to pin 9 of IC17A
where it should appear as a clearly defined 6MHz square wave (0). 4)
should appear from the driver Q1 to supply IC2 pin 6. Check that the
clock signals, 4) and appear at all the expected points shown on the
circuit diagram. If not, check for loading caused by failed IC's and
track short-circuits. Pin 11 of IC19D should also be generating a
delayed clock required for the NMISERV circuit. If no delayed clock
is found, check the values of C9 and R9.
Using an oscilloscope, check that a 12MHz signal is being generated
at pin 13 of IC22D. If not, check the crystal X1, resistor values and
operation of inverters IC24D/E. Trace the signal to pin 9 of IC17A
where it should appear as a clearly defined 6MHz square wave (0). 4)
should appear from the driver Q1 to supply IC2 pin 6. Check that the
clock signals, 4) and appear at all the expected points shown on the
circuit diagram. If not, check for loading caused by failed IC's and
track short-circuits. Pin 11 of IC19D should also be generating a
delayed clock required for the NMISERV circuit. If no delayed clock
is found, check the values of C9 and R9.
6.3.2 RAS/CAS Generator Circuits
Both of these are best traced back from the RAM. RAS is always
present and should be seen at TP8 and also inverted at pin 3 of
IC21A. If only one appears, then check for loading, either on the
address buffers or on the DRAMS.
present and should be seen at TP8 and also inverted at pin 3 of
IC21A. If only one appears, then check for loading, either on the
address buffers or on the DRAMS.
RAS is generated by both IC18A and IC17B (SUE and CPOP signals
respectively), independently of each other, but both are required to
be operating for full RAS ability. RAS may therefore be appearing due
to only one of the two Dtypes working, so check that pins 1 and 2 of
both IC20A and IC21A are operating. If not, check the operation of
the Dtypes according to inputs; RAS wi11 fail if the CPU is not
operating as it requires Ml, and MREQ, as we11 as the clock signal.
respectively), independently of each other, but both are required to
be operating for full RAS ability. RAS may therefore be appearing due
to only one of the two Dtypes working, so check that pins 1 and 2 of
both IC20A and IC21A are operating. If not, check the operation of
the Dtypes according to inputs; RAS wi11 fail if the CPU is not
operating as it requires Ml, and MREQ, as we11 as the clock signal.
The operation of CAS is dependant upon the functioning of RAS and
also the correct decoding of a memory access. Check that memory RD, W
or Instruction Fetch (Ml) signals appear then check that this is
properly decoded from IC23B to IC23C via IC20C, and not disabled by
an incorrect signal from 1C23D.
also the correct decoding of a memory access. Check that memory RD, W
or Instruction Fetch (Ml) signals appear then check that this is
properly decoded from IC23B to IC23C via IC20C, and not disabled by
an incorrect signal from 1C23D.
6.3.3 Wait State Generator
IC2 pin 24 should predominantly be high; WAIT should only be active
under two conditions:
under two conditions:
i)
During ROM read, TP2 goes low for approximately 0.25sec. This is
visible as a low on a logic probe applied to IC16A pin 2 after
the BREAK key has been pressed.
visible as a low on a logic probe applied to IC16A pin 2 after
the BREAK key has been pressed.
ii) When PCS and PCS occur simultaneously; this WAIT pulse is
generated frequently during data transfer via the Tube. Note
that, in this second case, the WAIT signal is produced by the
desync. logic.
that, in this second case, the WAIT signal is produced by the
desync. logic.