Acorn Products Z80 SECOND PROCESSSOR 409 用户手册
6.3.5 Desynchronising Logic and PCS Disable HCS
After power-up, check that PCS is active at pin 18 of IC1. If not,
then either the Tube 1C1 or IC29 has failed on the second processor
side, there is a ribbon cable/connector fault, or the Host is faulty.
PCS
then either the Tube 1C1 or IC29 has failed on the second processor
side, there is a ribbon cable/connector fault, or the Host is faulty.
PCS
After pressing BREAK, check that a low signal appears simultaneously
at pins 1 and 2 of IC22A and that this appears at pin 3. Check that a
low then appears at pin 21 of IC1; if not, the
Desync. logic circuit is faulty. Check the clock signal at pin 11 of
IC30 and the inverted clock signal at pin 3. Whilst referring to the
Circuit Description, check that a11 signals are operating correctly in
the Desync. logic circuit.
at pins 1 and 2 of IC22A and that this appears at pin 3. Check that a
low then appears at pin 21 of IC1; if not, the
Desync. logic circuit is faulty. Check the clock signal at pin 11 of
IC30 and the inverted clock signal at pin 3. Whilst referring to the
Circuit Description, check that a11 signals are operating correctly in
the Desync. logic circuit.
With HCS checked to be functioning correctly, PCS REQ, via IC29A,
should always reach Pin 12 of IC30B when HCS is high. If not, check
operation of IC30A and that pin 5 of IC30A only produces a low signal
when HCS is active.
should always reach Pin 12 of IC30B when HCS is high. If not, check
operation of IC30A and that pin 5 of IC30A only produces a low signal
when HCS is active.
6.3.6 NMISERV
When an active signal appears at pin 17 of IC2 (NMI), the address
lines should be seen to address 066H (instruction fetch). This should
decode through IC26/27 to give the NMISERV signal. Failure of this
circuit wi11 prevent disk access. If this occurs, check 0D clock
circuit, that NMI from IC2 pin 17 appears at pin 5 of IC21B and that
NMISERV from pin 9 of IC27 appears at pin 4 of IC15A and IC21D pin 12.
Check for broken tracks and replace IC's 26 and 27 if necessary.
lines should be seen to address 066H (instruction fetch). This should
decode through IC26/27 to give the NMISERV signal. Failure of this
circuit wi11 prevent disk access. If this occurs, check 0D clock
circuit, that NMI from IC2 pin 17 appears at pin 5 of IC21B and that
NMISERV from pin 9 of IC27 appears at pin 4 of IC15A and IC21D pin 12.
Check for broken tracks and replace IC's 26 and 27 if necessary.
6.3.7 Interrupt OFEH
When operating the Boot ROM, the interrupt vector 0FEP from IC28 wi11
be read. Check the operation of IC28, that M1 and IORQ are appearing,
that the buffer inputs are correctly tied (high or low) and that the
buffer output of "FE" is appearing upon request; if not, check tracks
and power rails. Replace IC28 if necessary.
be read. Check the operation of IC28, that M1 and IORQ are appearing,
that the buffer inputs are correctly tied (high or low) and that the
buffer output of "FE" is appearing upon request; if not, check tracks
and power rails. Replace IC28 if necessary.
6.3.8 DRAMS (Dynamic RAM IC's)
The fo11owing should be performed for each DRAM in turn (IC's 6 -13):
Check the power supply pins, +5v to pin 8 and Ov to pin 16. Check
that RAS, CAS, and W are all appearing, then make sure that address
buffers become enabled (active low) at pins 1 and 19 of 1C's 4 and 5,
and providing active address lines to the DRAMS. Check that no
The fo11owing should be performed for each DRAM in turn (IC's 6 -13):
Check the power supply pins, +5v to pin 8 and Ov to pin 16. Check
that RAS, CAS, and W are all appearing, then make sure that address
buffers become enabled (active low) at pins 1 and 19 of 1C's 4 and 5,
and providing active address lines to the DRAMS. Check that no