Texas Instruments TMS320C642x DSP 用户手册
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Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 0, bank 0
Row 0, bank 1
Row 0, bank 2
Row 0, bank P
Row 1, bank 1
Row 1, bank 0
Row 1, bank 2
Row 1, bank P
Row N, bank 2
Row N, bank 1
Row N, bank 0
Row N, bank P
Peripheral Architecture
Figure 12. Logical Address-to-DDR2 SDRAM Address Map
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
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DDR2 Memory Controller
SPRUEM4A – November 2007