Fujitsu mb91192 用户手册

CHAPTER 4 External Bus Interface

4.6.1

Relationship between Data Bus Width and Control Signal

The control signal of WR0 to WR1 always supports the byte position of the data bus 1:1
regardless of big endian/little endian is used, or the data bus width.

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The Relationship between the Data Bus Width and Control Signal

In this section, the byte position of the data bus for this product used by the data bus width that has been

set, and control signals that support it are summarized.

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The time division input/output bus interface

Figure 4.6-1 Data bus width and control signals under the time division input/output bus interface

Data bus

Control siganal

Data bus

WR0

WR1

a) 16 bit bus width

b) 8 bit bus width

(D15 to 0: unused)

(D23 to 0: unused)

Output address

A15 to 8

A7 to 0

Output address

A7 to 0

D31

D16

WR0