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CHAPTER 3  CPU

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It is necessary to arrange the program of the FR20 series in the address of the multiple of two. Bit 0 of the

program counter (PC) is set to "0" when updating the PC in line with execution of the command. It may be

"1" only when an odd address is specified as the branch destination address. Even in that case, bit 0 is

invalid, and the command must be placed in the address of the multiple of two.

There is no odd number address exception.

■

In the FR20 series, when data is accessed, forced alignment is applied to the address depending on its width

as follows.

•

Word Access:

An address must be a multiple of 4. (The lowest 2-bit is forcibly "00".)

•

Half-word access: An address must be a multiple of 2. (The lowest bit is forcibly "0".)

•

Byte Access:

-

When word or half-word data is accessed, "0" is forcibly set to some bits, which are the calculation results

of the effective address. For example, in the @(R13,Ri) addressing mode, the register before addition is

used for calculations as it is (even though the lowest bit is 1), and the lower bits of the addition results will

be masked. A register before calculation is not masked.

(example) LD @(R13,R2),R0 

R13    

00002222

H

R2     

00000003

H

Addition result     00002225

H

Lower 2-bit forcibly mask

Address pin     00002224

H