Fujitsu mb91192 用户手册
67
3.12.5
Watchdog Reset Generation Delay Register (WPR)
This register clears the flip-flop for the watchdog timer. Using this register postpones
generation of the watchdog reset.
generation of the watchdog reset.
■
Watchdog Reset Generation Delay Register (WPR)
Figure 3.12-7 Watchdog reset generation delay register (WPR)
[bit7 to 0]
Writing A5
H
, 5A
H
continuously to this register clears the flip-flop for the watchdog timer to "0"
immediately after 5A
H
, and postpones generation of the watchdog reset.
The reading value of this register is irregular. There is no time limit between A5
H
and 5A
H
, but if
writing both data is not finished within the period as per the following table, a watchdog reset is
generated. However, clearing is automatically carried out under stop/sleep mode, so when these
conditions are generated, the watchdog reset is automatically postponed.
Note:
φ is twice as large as X0 when GCR CHC is 1, and is one time as large as X0 when GCR CHC is 0.
D7 D6 D5 D4 D3 D2 D1 D0 XXXX
XXXX
B
7
6
4
5
4
3
2
1
0
Initial value
W
W
W
W
W
W
W
W
Address: 000485
H
Access
bit
Table 3.12-5 Watchdog timer cycle specified by WT1 and WT2
WT1 WT0
Writing spacing to at least
necessary for control generation of
watchdog reset WPR
Time from 5A
H
final writing in WPR to
generation of watchdog reset
0 0
φ × 2
15
φ × 2
15
to
φ × 2
16
0 1
φ × 2
17
φ × 2
17
to
φ × 2
18
1 0
φ × 2
19
φ × 2
19
to
φ × 2
20
1 1
φ × 2
21
φ × 2
21
to
φ × 2
22