Motorola MC68HC908MR32 用户手册
Clock Generator Module (CGM)
Functional Description
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
Advance Information
MOTOROLA
Clock Generator Module (CGM)
113
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
8.4.2.1 PLL Circuits
The PLL consists of these circuits:
•
Voltage-controlled oscillator (VCO)
•
Modulo VCO frequency divider
•
Phase detector
•
Loop filter
•
Lock detector
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$005C
PLL Control Register
(PCTL)
Read:
PLLIE
PLLF
PLLON
BCS
1
1
1
1
Write:
R
R
R
R
R
Reset:
0
0
1
0
1
1
1
1
$005D
PLL Bandwidth Control Register
(PBWC)
Read:
AUTO
LOCK
ACQ
XLD
0
0
0
0
Write:
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
$005E
PLL Programming Register
(PPG)
Read:
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
Write:
Reset:
0
1
1
0
0
1
1
0
R
= Reserved
Figure 8-2. CGM I/O Register Summary