用户手册 — Motorola MC68HC908MR32

目录

• Revision History

  4
• List of Sections

  5
• Table of Contents

  7
• List of Figures

  21
• List of Tables

  27
• Section 1. General Description

  29
  • 1.1 Contents

    29
  • 1.2 Introduction

    30
  • 1.3 Features

    30
  • 1.4 MCU Block Diagram

    31
  • 1.5 Pin Assignments

    33
    • 1.5.1 Power Supply Pins (VDD and VSS)

      35
    • 1.5.2 Oscillator Pins (OSC1 and OSC2)

      35
    • 1.5.3 External Reset Pin (RST)

      35
    • 1.5.4 External Interrupt Pin (IRQ)

      36
    • 1.5.5 CGM Power Supply Pins (VDDA and VSSA)

      36
    • 1.5.6 External Filter Capacitor Pin (CGMXFC)

      36
    • 1.5.7 Analog Power Supply Pins (VDDA and VSSA)

      36
    • 1.5.8 ADC Voltage Decoupling Capacitor Pin (VREFH)

      36
    • 1.5.9 ADC Voltage Reference Low Pin (VREFL)

      36
    • 1.5.10 Port A Input/Output (I/O) Pins (PTA7–PTA0)

      37
    • 1.5.11 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)

      37
    • 1.5.12 Port C I/O Pins (PTC6–PTC2 and PTC1/ATD9–PTC0/ATD8)

      37
    • 1.5.13 Port D Input-Only Pins (PTD6/IS3–PTD4/IS1 and PTD3/FAULT4–PTD0/FAULT1)

      37
    • 1.5.14 PWM Pins (PWM6–PWM1)

      37
    • 1.5.15 PWM Ground Pin (PWMGND)

      38
    • 1.5.16 Port E I/O Pins (PTE7/TCH3A–PTE3/TCLKA and PTE2/TCH1B–PTE0/TCLKB)

      38
    • 1.5.17 Port F I/O Pins (PTF5/TxD–PTF4/RxD and PTF3/MISO–PTF0/SPSCK)

      38
• Section 2. Memory Map

  39
  • 2.1 Contents

    39
  • 2.2 Introduction

    39
  • 2.3 Unimplemented Memory Locations

    39
  • 2.4 Reserved Memory Locations

    40
  • 2.5 I/O Section

    40
  • 2.6 Monitor ROM

    53
• Section 3. Random-Access Memory (RAM)

  55
  • 3.1 Contents

    55
  • 3.2 Introduction

    55
  • 3.3 Functional Description

    55
• Section 4. FLASH Memory

  57
  • 4.1 Contents

    57
  • 4.2 Introduction

    57
  • 4.3 Functional Description

    58
  • 4.4 FLASH Control Register

    59
  • 4.5 FLASH Page Erase Operation

    60
  • 4.6 FLASH Mass Erase Operation

    61
  • 4.7 FLASH Program/Read Operation

    62
  • 4.8 FLASH Block Protection

    64
  • 4.9 FLASH Block Protect Register

    65
  • 4.10 Wait Mode

    66
  • 4.11 Stop Mode

    66
• Section 5. Configuration Register (CONFIG)

  67
  • 5.1 Contents

    67
  • 5.2 Introduction

    67
  • 5.3 Functional Description

    67
  • 5.4 Configuration Register

    68
• Section 6. Central Processor Unit (CPU)

  71
  • 6.1 Contents

    71
  • 6.2 Introduction

    71
  • 6.3 Features

    72
  • 6.4 CPU Registers

    72
    • 6.4.1 Accumulator

      73
    • 6.4.2 Index Register

      73
    • 6.4.3 Stack Pointer

      74
    • 6.4.4 Program Counter

      75
    • 6.4.5 Condition Code Register

      75
  • 6.5 Arithmetic/Logic Unit (ALU)

    77
  • 6.6 Low-Power Modes

    77
    • 6.6.1 Wait Mode

      78
    • 6.6.2 Stop Mode

      78
  • 6.7 CPU During Break Interrupts

    78
  • 6.8 Instruction Set Summary

    79
  • 6.9 Opcode Map

    86
• Section 7. System Integration Module (SIM)

  89
  • 7.1 Contents

    89
  • 7.2 Introduction

    90
  • 7.3 SIM Bus Clock Control and Generation

    92
    • 7.3.1 Bus Timing

      93
    • 7.3.2 Clock Startup from POR or LVI Reset

      93
    • 7.3.3 Clocks in Wait Mode

      93
  • 7.4 Reset and System Initialization

    93
    • 7.4.1 External Pin Reset

      94
    • 7.4.2 Active Resets from Internal Sources

      95
      • 7.4.2.1 Power-On Reset (POR)

        96
      • 7.4.2.2 Computer Operating Properly (COP) Reset

        97
      • 7.4.2.3 Illegal Opcode Reset

        97
      • 7.4.2.4 Illegal Address Reset

        97
      • 7.4.2.5 Forced Monitor Mode Entry Reset (MENRST)

        98
      • 7.4.2.6 Low-Voltage Inhibit (LVI) Reset

        98
  • 7.5 SIM Counter

    98
    • 7.5.1 SIM Counter During Power-On Reset

      98
    • 7.5.2 SIM Counter and Reset States

      98
  • 7.6 Exception Control

    99
    • 7.6.1 Interrupts

      99
      • 7.6.1.1 Hardware Interrupts

        101
      • 7.6.1.2 Software Interrupt (SWI) Instruction

        102
    • 7.6.2 Reset

      102
  • 7.7 Low-Power Mode

    102
    • 7.7.1 Wait Mode

      102
    • 7.7.2 Stop Mode

      104
  • 7.8 SIM Registers

    104
    • 7.8.1 SIM Break Status Register

      104
    • 7.8.2 SIM Reset Status Register

      106
    • 7.8.3 SIM Break Flag Control Register

      107
• Section 8. Clock Generator Module (CGM)

  109
  • 8.1 Contents

    109
  • 8.2 Introduction

    110
  • 8.3 Features

    110
  • 8.4 Functional Description

    111
    • 8.4.1 Crystal Oscillator Circuit

      111
    • 8.4.2 Phase-Locked Loop Circuit (PLL)

      113
      • 8.4.2.1 PLL Circuits

        113
      • 8.4.2.2 Acquisition and Tracking Modes

        115
      • 8.4.2.3 Manual and Automatic PLL Bandwidth Modes

        115
      • 8.4.2.4 Programming the PLL

        117
      • 8.4.2.5 Special Programming Exceptions

        119
    • 8.4.3 Base Clock Selector Circuit

      119
    • 8.4.4 CGM External Connections

      119
  • 8.5 I/O Signals

    121
    • 8.5.1 Crystal Amplifier Input Pin (OSC1)

      121
    • 8.5.2 Crystal Amplifier Output Pin (OSC2)

      121
    • 8.5.3 External Filter Capacitor Pin (CGMXFC)

      121
    • 8.5.4 PLL Analog Power Pin (VDDA)

      122
    • 8.5.5 Oscillator Enable Signal (SIMOSCEN)

      122
    • 8.5.6 Crystal Output Frequency Signal (CGMXCLK)

      122
    • 8.5.7 CGM Base Clock Output (CGMOUT)

      122
    • 8.5.8 CGM CPU Interrupt (CGMINT)

      122
  • 8.6 CGM Registers

    123
    • 8.6.1 PLL Control Register

      124
    • 8.6.2 PLL Bandwidth Control Register

      126
    • 8.6.3 PLL Programming Register

      128
  • 8.7 Interrupts

    129
  • 8.8 Wait Mode

    130
  • 8.9 Acquisition/Lock Time Specifications

    130
    • 8.9.1 Acquisition/Lock Time Definitions

      130
    • 8.9.2 Parametric Influences on Reaction Time

      132
    • 8.9.3 Choosing a Filter Capacitor

      133
    • 8.9.4 Reaction Time Calculation

      133
• Section 9. Pulse-Width Modulator for Motor Control (PWMMC)

  135
  • 9.1 Contents

    135
  • 9.2 Introduction

    136
  • 9.3 Features

    137
  • 9.4 Timebase

    141
    • 9.4.1 Resolution

      141
    • 9.4.2 Prescaler

      143
  • 9.5 PWM Generators

    143
    • 9.5.1 Load Operation

      143
    • 9.5.2 PWM Data Overflow and Underflow Conditions

      147
  • 9.6 Output Control

    147
    • 9.6.1 Selecting Six Independent PWMs or Three Complementary PWM Pairs

      147
    • 9.6.2 Dead-Time Insertion

      149
    • 9.6.3 Top/Bottom Correction with Motor Phase Current Polarity Sensing

      153
    • 9.6.4 Output Polarity

      157
    • 9.6.5 PWM Output Port Control

      158
  • 9.7 Fault Protection

    160
    • 9.7.1 Fault Condition Input Pins

      161
      • 9.7.1.1 Fault Pin Filter

        161
      • 9.7.1.2 Automatic Mode

        163
      • 9.7.1.3 Manual Mode

        164
    • 9.7.2 Software Output Disable

      165
    • 9.7.3 Output Port Control

      166
  • 9.8 Initialization and the PWMEN Bit

    166
  • 9.9 PWM Operation in Wait Mode

    168
  • 9.10 Control Logic Block

    168
    • 9.10.1 PWM Counter Registers

      168
    • 9.10.2 PWM Counter Modulo Registers

      169
    • 9.10.3 PWMx Value Registers

      170
    • 9.10.4 PWM Control Register 1

      171
    • 9.10.5 PWM Control Register 2

      173
    • 9.10.6 Dead-Time Write-Once Register

      176
    • 9.10.7 PWM Disable Mapping Write-Once Register

      176
    • 9.10.8 Fault Control Register

      177
    • 9.10.9 Fault Status Register

      179
    • 9.10.10 Fault Acknowledge Register

      180
    • 9.10.11 PWM Output Control Register

      182
  • 9.11 PWM Glossary

    183
• Section 10. Monitor ROM (MON)

  185
  • 10.1 Contents

    185
  • 10.2 Introduction

    185
  • 10.3 Features

    186
  • 10.4 Functional Description

    186
    • 10.4.1 Entering Monitor Mode

      188
      • 10.4.1.1 Normal Monitor Mode

        188
      • 10.4.1.2 Forced Monitor Mode

        190
    • 10.4.2 Data Format

      191
    • 10.4.3 Echoing

      191
    • 10.4.4 Break Signal

      192
    • 10.4.5 Commands

      192
    • 10.4.6 Baud Rate

      196
  • 10.5 Security

    196
• Section 11. Timer Interface A (TIMA)

  199
  • 11.1 Contents

    199
  • 11.2 Introduction

    200
  • 11.3 Features

    200
  • 11.4 Functional Description

    204
    • 11.4.1 TIMA Counter Prescaler

      204
    • 11.4.2 Input Capture

      204
    • 11.4.3 Output Compare

      206
      • 11.4.3.1 Unbuffered Output Compare

        206
      • 11.4.3.2 Buffered Output Compare

        207
    • 11.4.4 Pulse-Width Modulation (PWM)

      208
      • 11.4.4.1 Unbuffered PWM Signal Generation

        209
      • 11.4.4.2 Buffered PWM Signal Generation

        210
      • 11.4.4.3 PWM Initialization

        211
  • 11.5 Interrupts

    212
  • 11.6 Wait Mode

    212
  • 11.7 I/O Signals

    213
    • 11.7.1 TIMA Clock Pin (PTE3/TCLKA)

      213
    • 11.7.2 TIMA Channel I/O Pins (PTE4/TCH0A–PTE7/TCH3A)

      213
  • 11.8 I/O Registers

    214
    • 11.8.1 TIMA Status and Control Register

      214
    • 11.8.2 TIMA Counter Registers

      216
    • 11.8.3 TIMA Counter Modulo Registers

      217
    • 11.8.4 TIMA Channel Status and Control Registers

      217
    • 11.8.5 TIMA Channel Registers

      222
• Section 12. Timer Interface B (TIMB)

  225
  • 12.1 Contents

    225
  • 12.2 Introduction

    226
  • 12.3 Features

    226
  • 12.4 Functional Description

    226
    • 12.4.1 TIMB Counter Prescaler

      227
    • 12.4.2 Input Capture

      229
    • 12.4.3 Output Compare

      230
      • 12.4.3.1 Unbuffered Output Compare

        230
      • 12.4.3.2 Buffered Output Compare

        231
    • 12.4.4 Pulse-Width Modulation (PWM)

      232
      • 12.4.4.1 Unbuffered PWM Signal Generation

        233
      • 12.4.4.2 Buffered PWM Signal Generation

        234
      • 12.4.4.3 PWM Initialization

        234
  • 12.5 Interrupts

    236
  • 12.6 Wait Mode

    236
  • 12.7 I/O Signals

    236
    • 12.7.1 TIMB Clock Pin (PTE4/ATD12)

      237
    • 12.7.2 TIMB Channel I/O Pins (PTE1/TCH0B–PTE2/TCH1B)

      237
  • 12.8 I/O Registers

    237
    • 12.8.1 TIMB Status and Control Register

      238
    • 12.8.2 TIMB Counter Registers

      240
    • 12.8.3 TIMB Counter Modulo Registers

      241
    • 12.8.4 TIMB Channel Status and Control Registers

      242
    • 12.8.5 TIMB Channel Registers

      245
• Section 13. Serial Peripheral Interface Module (SPI)

  247
  • 13.1 Contents

    247
  • 13.2 Introduction

    248
  • 13.3 Features

    248
  • 13.4 Pin Name Conventions

    248
  • 13.5 Functional Description

    249
    • 13.5.1 Master Mode

      249
    • 13.5.2 Slave Mode

      252
  • 13.6 Transmission Formats

    253
    • 13.6.1 Clock Phase and Polarity Controls

      253
    • 13.6.2 Transmission Format When CPHA = 0

      253
    • 13.6.3 Transmission Format When CPHA=1

      255
    • 13.6.4 Transmission Initiation Latency

      256
  • 13.7 Error Conditions

    258
    • 13.7.1 Overflow Error

      258
    • 13.7.2 Mode Fault Error

      260
  • 13.8 Interrupts

    262
  • 13.9 Resetting the SPI

    264
  • 13.10 Queuing Transmission Data

    264
  • 13.11 Low-Power Mode

    266
  • 13.12 I/O Signals

    266
    • 13.12.1 MISO (Master In/Slave Out)

      267
    • 13.12.2 MOSI (Master Out/Slave In)

      267
    • 13.12.3 SPSCK (Serial Clock)

      267
    • 13.12.4 SS (Slave Select)

      268
    • 13.12.5 VSS (Clock Ground)

      269
  • 13.13 I/O Registers

    269
    • 13.13.1 SPI Control Register

      270
    • 13.13.2 SPI Status and Control Register

      272
    • 13.13.3 SPI Data Register

      275
• Section 14. Serial Communications Interface Module (SCI)

  277
  • 14.1 Contents

    277
  • 14.2 Introduction

    278
  • 14.3 Features

    278
  • 14.4 Functional Description

    279
    • 14.4.1 Data Format

      281
    • 14.4.2 Transmitter

      281
      • 14.4.2.1 Character Length

        281
      • 14.4.2.2 Character Transmission

        281
      • 14.4.2.3 Break Characters

        283
      • 14.4.2.4 Idle Characters

        283
      • 14.4.2.5 Inversion of Transmitted Output

        284
      • 14.4.2.6 Transmitter Interrupts

        284
    • 14.4.3 Receiver

      284
      • 14.4.3.1 Character Length

        284
      • 14.4.3.2 Character Reception

        286
      • 14.4.3.3 Data Sampling

        286
      • 14.4.3.4 Framing Errors

        288
      • 14.4.3.5 Receiver Wakeup

        288
      • 14.4.3.6 Receiver Interrupts

        289
      • 14.4.3.7 Error Interrupts

        290
  • 14.5 Wait Mode

    290
  • 14.6 SCI During Break Module Interrupts

    291
  • 14.7 I/O Signals

    291
    • 14.7.1 PTF5/TxD (Transmit Data)

      291
    • 14.7.2 PTF4/RxD (Receive Data)

      292
  • 14.8 I/O Registers

    292
    • 14.8.1 SCI Control Register 1

      292
    • 14.8.2 SCI Control Register 2

      295
    • 14.8.3 SCI Control Register 3

      298
    • 14.8.4 SCI Status Register 1

      299
    • 14.8.5 SCI Status Register 2

      303
    • 14.8.6 SCI Data Register

      304
    • 14.8.7 SCI Baud Rate Register

      304
• Section 15. Input/Output (I/O) Ports

  307
  • 15.1 Contents

    307
  • 15.2 Introduction

    307
  • 15.3 Port A

    310
    • 15.3.1 Port A Data Register

      310
    • 15.3.2 Data Direction Register A

      310
  • 15.4 Port B

    312
    • 15.4.1 Port B Data Register

      312
    • 15.4.2 Data Direction Register B

      312
  • 15.5 Port C

    314
    • 15.5.1 Port C Data Register

      314
    • 15.5.2 Data Direction Register C

      314
  • 15.6 Port D

    316
  • 15.7 Port E

    317
    • 15.7.1 Port E Data Register

      317
    • 15.7.2 Data Direction Register E

      318
  • 15.8 Port F

    319
    • 15.8.1 Port F Data Register

      319
    • 15.8.2 Data Direction Register F

      320
• Section 16. Computer Operating Properly (COP)

  323
  • 16.1 Contents

    323
  • 16.2 Introduction

    323
  • 16.3 Functional Description

    324
  • 16.4 I/O Signals

    325
    • 16.4.1 CGMXCLK

      325
    • 16.4.2 COPCTL Write

      325
    • 16.4.3 Power-On Reset

      325
    • 16.4.4 Internal Reset

      326
    • 16.4.5 Reset Vector Fetch

      326
    • 16.4.6 COPD (COP Disable)

      326
  • 16.5 COP Control Register

    326
  • 16.6 Interrupts

    326
  • 16.7 Monitor Mode

    327
  • 16.8 Wait Mode

    327
  • 16.9 Stop Mode

    327
• Section 17. External Interrupt (IRQ)

  329
  • 17.1 Contents

    329
  • 17.2 Introduction

    329
  • 17.3 Features

    329
  • 17.4 Functional Description

    330
  • 17.5 IRQ Pin

    333
  • 17.6 IRQ Status and Control Register

    334
• Section 18. Low-Voltage Inhibit (LVI)

  335
  • 18.1 Contents

    335
  • 18.2 Introduction

    335
  • 18.3 Features

    335
  • 18.4 Functional Description

    336
    • 18.4.1 Polled LVI Operation

      337
    • 18.4.2 Forced Reset Operation

      337
    • 18.4.3 False Reset Protection

      337
    • 18.4.4 LVI Trip Selection

      338
  • 18.5 LVI Status and Control Register

    338
  • 18.6 LVI Interrupts

    339
  • 18.7 Wait Mode

    339
  • 18.8 Stop Mode

    340
• Section 19. Analog-to-Digital Converter (ADC)

  341
  • 19.1 Contents

    341
  • 19.2 Introduction

    342
  • 19.3 Features

    342
  • 19.4 Functional Description

    342
    • 19.4.1 ADC Port I/O Pins

      343
    • 19.4.2 Voltage Conversion

      344
    • 19.4.3 Conversion Time

      344
    • 19.4.4 Continuous Conversion

      345
    • 19.4.5 Result Justification

      345
    • 19.4.6 Monotonicity

      346
  • 19.5 Interrupts

    346
  • 19.6 Wait Mode

    347
  • 19.7 I/O Signals

    347
    • 19.7.1 ADC Analog Power Pin (VDDAD)

      347
    • 19.7.2 ADC Analog Ground Pin (VSSAD)

      347
    • 19.7.3 ADC Voltage Reference Pin (VREFH)

      347
    • 19.7.4 ADC Voltage Reference Low Pin (VREFL)

      348
    • 19.7.5 ADC Voltage In (ADVIN)

      348
    • 19.7.6 ADC External Connections

      348
      • 19.7.6.1 VREFH and VREFL

        348
      • 19.7.6.2 ANx

        348
      • 19.7.6.3 Grounding

        349
  • 19.8 I/O Registers

    349
    • 19.8.1 ADC Status and Control Register

      349
    • 19.8.2 ADC Data Register High

      352
    • 19.8.3 ADC Data Register Low

      353
    • 19.8.4 ADC Clock Register

      354
• Section 20. Power-On Reset (POR)

  357
  • 20.1 Contents

    357
  • 20.2 Introduction

    357
  • 20.3 Functional Description

    357
• Section 21. Break Module (BRK)

  359
  • 21.1 Contents

    359
  • 21.2 Introduction

    359
  • 21.3 Features

    360
  • 21.4 Functional Description

    360
    • 21.4.1 Flag Protection During Break Interrupts

      362
    • 21.4.2 CPU During Break Interrupts

      362
    • 21.4.3 TIM1 and TIM2 During Break Interrupts

      362
    • 21.4.4 COP During Break Interrupts

      362
  • 21.5 Low-Power Modes

    362
    • 21.5.1 Wait Mode

      362
    • 21.5.2 Stop Mode

      363
  • 21.6 Break Module Registers

    363
    • 21.6.1 Break Status and Control Register

      363
    • 21.6.2 Break Address Registers

      364
    • 21.6.3 Break Status Register

      365
    • 21.6.4 Break Flag Control Register

      366
• Section 22. Electrical Specifications

  367
  • 22.1 Contents

    367
  • 22.2 Introduction

    367
  • 22.3 Absolute Maximum Ratings

    368
  • 22.4 Functional Operating Range

    369
  • 22.5 Thermal Characteristics

    369
  • 22.6 DC Electrical Characteristics (VDD = 5.0 Vdc ± 10%)

    370
  • 22.7 FLASH Memory Characteristics

    371
  • 22.8 Control Timing (VDD = 5.0 Vdc ± 10%)

    372
  • 22.9 Serial Peripheral Interface Characteristics (VDD = 5.0 Vdc ± 10%)

    373
  • 22.10 TImer Interface Module Characteristics

    376
  • 22.11 Clock Generation Module Component Specifications

    376
  • 22.12 CGM Operating Conditions

    376
  • 22.13 CGM Acquisition/Lock Time Specifications

    377
  • 22.14 Analog-to-Digital Converter (ADC) Characteristics

    378
• Section 23. Mechanical Specifications

  379
  • 23.1 Contents

    379
  • 23.2 Introduction

    379
  • 23.3 64-Pin Plastic Quad Flat Pack (QFP)

    380
  • 23.4 56-Pin Shrink Dual In-Line Package (SDIP)

    381
• Section 24. Ordering Information

  383
  • 24.1 Contents

    383
  • 24.2 Introduction

    383
  • 24.3 Order Numbers

    383
• Appendix A. MC68HC908MR16

  385
  • A.1 Contents

    385
  • A.2 Introduction

    385
  • A.3 Memory Map

    386