用户手册目录Legal Lines and Disclaimers2Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor11.0 Introduction261.1 About This Document261.1.1 How to Read This Document261.2 Other Relevant Documents261.3 Terminology and Conventions261.3.1 Number Representation261.3.2 Acronyms and Terminology272.0 Overview of Product Line302.1 Intel XScale® Microarchitecture Processor352.1.1 Intel XScale® Processor Overview362.1.1.1 ARM* Compatibility362.1.1.2 Multiply/Accumulate (MAC)362.1.1.3 Memory Management372.1.1.4 Instruction Cache372.1.1.5 Branch Target Buffer372.1.1.6 Data Cache372.1.1.7 Intel XScale® Processor Performance Monitoring382.2 Network Processor Engines (NPE)382.3 Internal Bus392.4 MII Interfaces392.5 AHB Queue Manager392.6 UTOPIA 2402.7 USB v1.1402.8 PCI402.9 Memory Controller402.10 Expansion Bus412.11 High-Speed Serial Interfaces412.12 Universal Asynchronous Receiver Transceiver422.13 GPIO422.14 Interrupt Controller422.15 Timers422.16 JTAG433.0 Intel XScale® Processor443.1 Memory Management Unit443.1.1 Memory Attributes453.1.1.1 Page (P) Attribute Bit453.1.1.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits453.1.2 Interaction of the MMU, Instruction Cache, and Data Cache473.1.3 MMU Control483.1.3.1 Invalidate (Flush) Operation483.1.3.2 Enabling/Disabling483.1.3.3 Locking Entries493.1.3.4 Round-Robin Replacement Algorithm513.2 Instruction Cache523.2.1 Operation When Instruction Cache is Enabled523.2.1.1 Instruction-Cache ‘Miss’533.2.1.2 Instruction-Cache Line-Replacement Algorithm543.2.1.3 Instruction-Cache Coherence553.3 Branch Target Buffer583.3.1 Branch Target Buffer (BTB) Operation583.3.1.1 Reset593.4 Data Cache603.4.1 Data Cache Overview603.4.2 Cacheability633.4.3 Reconfiguring the Data Cache as Data RAM683.5 Configuration733.5.1 CP15 Registers753.5.1.1 Register 0: ID and Cache Type Registers763.5.1.2 Register 1: Control and Auxiliary Control Registers773.5.1.3 Register 2: Translation Table Base Register793.5.1.4 Register 3: Domain Access Control Register803.5.1.5 Register 4: Reserved803.5.1.6 Register 5: Fault Status Register803.5.1.7 Register 6: Fault Address Register813.5.1.8 Register 7: Cache Functions813.5.1.9 Register 8: TLB Operations823.5.1.10 Register 9: Cache Lock Down823.5.1.11 Register 10: TLB Lock Down833.5.1.12 Register 11-12: Reserved843.5.1.13 Register 13: Process ID843.5.1.14 The PID Register Affect On Addresses843.5.1.15 Register 14: Breakpoint Registers853.5.1.16 Register 15: Coprocessor Access Register853.5.2 CP14 Registers863.5.2.1 Performance Monitoring Registers873.5.2.2 Clock and Power Management Registers873.5.2.3 Software Debug Registers883.6 Software Debug883.6.1 Definitions893.6.2 Debug Registers893.6.3 Debug Modes893.6.3.1 Halt Mode903.6.3.2 Monitor Mode903.6.4 Debug Control and Status Register (DCSR)903.6.4.1 Global Enable Bit (GE)913.6.4.2 Halt Mode Bit (H)913.6.4.3 Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR)923.6.4.4 Sticky Abort Bit (SA)923.6.4.5 Method of Entry Bits (MOE)923.6.4.6 Trace Buffer Mode Bit (M)923.6.4.7 Trace Buffer Enable Bit (E)923.6.5 Debug Exceptions923.6.5.1 Halt Mode933.6.5.2 Monitor Mode943.6.6 HW Breakpoint Resources953.6.6.1 Instruction Breakpoints953.6.6.2 Data Breakpoints963.6.7 Software Breakpoints983.6.8 Transmit/Receive Control Register983.6.8.1 RX Register Ready Bit (RR)993.6.8.2 Overflow Flag (OV)1003.6.8.3 Download Flag (D)1003.6.8.4 TX Register Ready Bit (TR)1003.6.8.5 Conditional Execution Using TXRXCTRL1013.6.9 Transmit Register1013.6.10 Receive Register1023.6.11 Debug JTAG Access1023.6.11.1 SELDCSR JTAG Command1023.6.11.2 SELDCSR JTAG Register1033.6.11.3 DBGTX JTAG Command1053.6.11.4 DBGTX JTAG Register1053.6.11.5 DBGRX JTAG Command1063.6.11.6 DBGRX JTAG Register1063.6.11.7 Debug JTAG Data Register Reset Values1093.6.12 Trace Buffer1093.6.12.1 Trace Buffer CP Registers1093.6.13 Trace Buffer Entries1113.6.13.1 Message Byte1113.6.13.2 Trace Buffer Usage1143.6.14 Downloading Code in ICache1163.6.14.1 LDIC JTAG Command1163.6.14.2 LDIC JTAG Data Register1173.6.14.3 LDIC Cache Functions1183.6.14.4 Loading IC During Reset1193.6.14.5 Dynamically Loading IC After Reset1233.6.14.6 Mini-Instruction Cache Overview1263.6.15 Halt Mode Software Protocol1263.6.15.1 Starting a Debug Session1263.6.15.2 Implementing a Debug Handler1283.6.15.3 Ending a Debug Session1313.6.16 Software Debug Notes and Errata1323.7 Performance Monitoring1333.7.1 Overview1333.7.2 Register Description1343.7.2.1 Clock Counter (CCNT)1343.7.2.2 Performance Count Registers1343.7.2.3 Performance Monitor Control Register1353.7.2.4 Interrupt Enable Register1363.7.2.5 Overflow Flag Status Register1363.7.2.6 Event Select Register1373.7.3 Managing the Performance Monitor1383.7.4 Performance Monitoring Events1393.7.4.1 Instruction Cache Efficiency Mode1403.7.4.2 Data Cache Efficiency Mode1403.7.4.3 Instruction Fetch Latency Mode1403.7.4.4 Data/Bus Request Buffer Full Mode1413.7.4.5 Stall/Write-Back Statistics1413.7.4.6 Instruction TLB Efficiency Mode1423.7.4.7 Data TLB Efficiency Mode1423.7.5 Multiple Performance Monitoring Run Statistics1423.7.6 Examples1423.8 Programming Model1443.8.1 ARM* Architecture Compatibility1443.8.2 ARM* Architecture Implementation Options1443.8.2.1 Big Endian versus Little Endian1443.8.2.2 26-Bit Architecture1453.8.2.3 Thumb1453.8.2.4 ARM* DSP-Enhanced Instruction Set1453.8.2.5 Base Register Update1453.8.3 Extensions to ARM* Architecture1463.8.3.1 DSP Coprocessor 0 (CP0)1463.8.3.2 New Page Attributes1523.8.3.3 Additions to CP15 Functionality1533.8.3.4 Event Architecture1543.9 Performance Considerations1593.9.1 Interrupt Latency1593.9.2 Branch Prediction1603.9.3 Addressing Modes1603.9.4 Instruction Latencies1603.9.4.1 Performance Terms1603.9.4.2 Branch Instruction Timings1623.9.4.3 Data Processing Instruction Timings1623.9.4.4 Multiply Instruction Timings1633.9.4.5 Saturated Arithmetic Instructions1653.9.4.6 Status Register Access Instructions1653.9.4.7 Load/Store Instructions1653.9.4.8 Semaphore Instructions1663.9.4.9 Coprocessor Instructions1663.9.4.10 Miscellaneous Instruction Timing1673.9.4.11 Thumb Instructions1673.10 Optimization Guide1673.10.1 Introduction1673.10.1.1 About This Section1683.10.2 Processors’ Pipeline1683.10.2.1 General Pipeline Characteristics1683.10.2.2 Instruction Flow Through the Pipeline1703.10.2.3 Main Execution Pipeline1713.10.2.4 Memory Pipeline1723.10.2.5 Multiply/Multiply Accumulate (MAC) Pipeline1733.10.3 Basic Optimizations1733.10.3.1 Conditional Instructions1733.10.3.2 Bit Field Manipulation1783.10.3.3 Optimizing the Use of Immediate Values1783.10.3.4 Optimizing Integer Multiply and Divide1783.10.3.5 Effective Use of Addressing Modes1793.10.4 Cache and Prefetch Optimizations1803.10.4.1 Instruction Cache1803.10.4.2 Data and Mini Cache1813.10.4.3 Cache Considerations1843.10.4.4 Prefetch Considerations1853.10.5 Instruction Scheduling1913.10.5.1 Scheduling Loads1913.10.5.2 Scheduling Data Processing Instructions1953.10.5.3 Scheduling Multiply Instructions1963.10.5.4 Scheduling SWP and SWPB Instructions1973.10.5.5 Scheduling the MRA and MAR Instructions (MRRC/MCRR)1973.10.5.6 Scheduling the MIA and MIAPH Instructions1983.10.5.7 Scheduling MRS and MSR Instructions1983.10.5.8 Scheduling CP15 Coprocessor Instructions1993.10.6 Optimizing C Libraries1993.10.7 Optimizations for Size1993.10.7.1 Space/Performance Trade Off1994.0 Network Processor Engines (NPE)2025.0 Internal Bus2045.1 Internal Bus Arbiters2045.1.1 Priority Mechanism2055.2 Memory Map2056.0 PCI Controller2086.1 PCI Controller Configured as Host2136.1.1 Example: Generating a PCI Configuration Write and Read2166.2 PCI Controller Configured as Option2186.3 Initializing PCI Controller Configuration and Status Registers for Data Transactions2196.3.1 Example: AHB Memory Base Address Register, AHB I/O Base Address Register, and PCI Memory Base Address Register2206.3.2 Example: PCI Memory Base Address Register and South-AHB Translation2226.4 Initializing the PCI Controller Configuration Registers2226.5 PCI Controller South AHB Transactions2256.6 PCI Controller Functioning as Bus Initiator2266.6.1 PCI Byte Enables2266.6.2 Initiated Type-0 Read Transaction2276.6.3 Initiated Type-0 Write Transaction2276.6.4 Initiated Type-1 Read Transaction2286.6.5 Initiated Type-1 Write Transaction2296.6.6 Initiated Memory Read Transaction2296.6.7 Initiated Memory Write Transaction2306.6.8 Initiated I/O Read Transaction2316.6.9 Initiated I/O Write Transaction2316.6.10 Initiated Burst Memory Read Transaction2326.6.11 Initiated Burst Memory Write Transaction2336.7 PCI Controller Functioning as Bus Target2346.8 PCI Controller DMA Controller2346.8.1 AHB to PCI DMA Channel Operation2386.8.2 PCI to AHB DMA Channel Operation2386.9 PCI Controller Door Bell Register2396.10 PCI Controller Interrupts2406.10.1 PCI Interrupt Generation2406.10.2 Internal Interrupt Generation2406.11 PCI Controller Endian Control2416.12 PCI Controller Clock and Reset Generation2486.13 PCI RCOMP Circuitry2496.14 Register Descriptions2496.14.1 PCI Configuration Registers2496.14.1.1 Device ID/Vendor ID Register2506.14.1.2 Status Register/Control Register2506.14.1.3 Class Code/Revision ID Register2526.14.1.4 BIST/Header Type/Latency Timer/Cache Line Register2526.14.1.5 Base Address 0 Register2536.14.1.6 Base Address 1 Register2546.14.1.7 Base Address 2 Register2546.14.1.8 Base Address 3 Register2556.14.1.9 Base Address 4 Register2556.14.1.10 Base Address 5 Register2566.14.1.11 Subsystem ID/Subsystem Vendor ID Register2566.14.1.12 Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register2576.14.1.13 Retry Timeout/TRDY Timeout Register2576.14.2 PCI Controller Configuration and Status Registers2586.14.2.1 PCI Controller Non-pre-fetch Address Register2596.14.2.2 PCI Controller Non-pre-fetch Command/Byte Enables Register2596.14.2.3 PCI Controller Non-Pre-fetch Write Data Register2606.14.2.4 PCI Controller Non-Pre-fetch Read Data Register2606.14.2.5 PCI Controller Configuration Port Address/Command/ Byte Enables Register2606.14.2.6 PCI Controller Configuration Port Write Data Register2616.14.2.7 PCI Controller Configuration Port Read Data Register2626.14.2.8 PCI Controller Control and Status Register2626.14.2.9 PCI Controller Interrupt Status Register2636.14.2.10 PCI Controller Interrupt Enable Register2646.14.2.11 DMA Control Register2656.14.2.12 AHB Memory Base Address Register2666.14.2.13 AHB I/O Base Address Register2666.14.2.14 PCI Memory Base Address Register2676.14.2.15 AHB Doorbell Register2676.14.2.16 PCI Doorbell Register2686.14.2.17 AHB to PCI DMA AHB Address Register 02686.14.2.18 AHB to PCI DMA PCI Address Register 02696.14.2.19 AHB to PCI DMA Length Register 02696.14.2.20 AHB to PCI DMA AHB Address Register 12706.14.2.21 AHB to PCI DMA PCI Address Register 12706.14.2.22 AHB to PCI DMA Length Register 12706.14.2.23 PCI to AHB DMA AHB Address Register 02716.14.2.24 PCI to AHB DMA PCI Address Register 02716.14.2.25 PCI to AHB DMA Length Register 02726.14.2.26 PCI to AHB DMA AHB Address Register 12726.14.2.27 PCI to AHB DMA PCI Address Register 12736.14.2.28 PCI to AHB DMA Length Register 12737.0 SDRAM Controller2767.1 SDRAM Memory Space2797.2 Initializing the SDRAM Controller2797.2.1 Initializing the SDRAM2837.3 SDRAM Memory Accesses2857.3.1 Read Transfer2857.3.1.1 Read Cycle Timing (CAS Latency of Two Cycles)2857.3.1.2 Read Burst Transfer (Interleaved AHB Reads)2867.3.2 Write Transfer2867.3.2.1 Write Transfer2867.4 Register Description2877.4.1 Configuration Register2877.4.2 Refresh Register2887.4.3 Instruction Register2888.0 Expansion Bus Controller2928.1 Expansion Bus Address Space2938.2 Chip Select Address Allocation2948.3 Address and Data Byte Steering2958.4 Expansion Bus Connections2978.5 Expansion Bus Interface Configuration2988.6 Using I/O Wait3018.7 Special Design Knowledge for Using HPI mode3038.8 Expansion Bus Interface Access Timing Diagrams3058.8.1 Intel® Multiplexed-Mode Write Access3058.8.2 Intel® Multiplexed-Mode Read Access3068.8.3 Intel® Simplex-Mode Write Access3078.8.4 Intel® Simplex-Mode Read Access3088.8.5 Motorola* Multiplexed-Mode Write Access3098.8.6 Motorola* Multiplexed-Mode Read Access3108.8.7 Motorola* Simplex-Mode Write Access3118.8.8 Motorola* Simplex-Mode Read Access3128.8.9 TI* HPI-8 Write Access3138.8.10 TI* HPI-8 Read Access3148.8.11 TI* HPI-16, Multiplexed-Mode Write Access3158.8.12 TI* HPI-16, Multiplexed-Mode Read Access3168.8.13 TI* HPI-16 Simplex-Mode Write Access3178.8.14 TI* HPI-16 Simplex-Mode Read Access3188.9 Register Descriptions3198.9.1 Timing and Control Registers for Chip Select 03198.9.2 Timing and Control Registers for Chip Select 13198.9.3 Timing and Control Registers for Chip Select 23208.9.4 Timing and Control Registers for Chip Select 33208.9.5 Timing and Control Registers for Chip Select 43208.9.6 Timing and Control Registers for Chip Select 53218.9.7 Timing and Control Registers for Chip Select 63218.9.8 Timing and Control Registers for Chip Select 73218.9.9 Configuration Register 03228.9.9.1 User-Configurable Field3248.9.10 Configuration Register 13248.10 Expansion Bus Controller Performance3269.0 AHB/APB Bridge32810.0 Universal Asynchronous Receiver Transceiver (UART)33210.1 High Speed UART33310.2 Configuring the UART33510.2.1 Setting the Baud Rate33510.2.2 Setting Data Bits/Stop Bits/Parity33610.2.3 Using the Modem Control Signals33810.2.4 UART Interrupts33910.3 Transmitting and Receiving UART Data34210.4 Register Descriptions34410.4.1 Receive Buffer Register34410.4.2 Transmit Holding Register34510.4.3 Divisor Latch Low Register34510.4.4 Divisor Latch High Register34610.4.5 Interrupt Enable Register34610.4.6 Interrupt Identification Register34710.4.7 FIFO Control Register34910.4.8 Line Control Register35010.4.9 Modem Control Register35210.4.10 Line Status Register35310.4.11 Modem Status Register35410.4.12 Scratch-Pad Register35510.4.13 Infrared Selection Register35610.5 Console UART35710.5.1 Register Description35710.5.1.1 Receive Buffer Register35810.5.1.2 Transmit Holding Register35810.5.1.3 Divisor Latch Low Register35910.5.1.4 Divisor Latch High Register35910.5.1.5 Interrupt Enable Register36010.5.1.6 Interrupt Identification Register36010.5.1.7 FIFO Control Register36210.5.1.8 Line Control Register36310.5.1.9 Modem Control Register36510.5.1.10 Line Status Register36610.5.1.11 Modem Status Register36710.5.1.12 Scratch-Pad Register36810.5.1.13 Infrared Selection Register36911.0 Internal Bus Performance Monitoring Unit (IBPMU)37211.1 Initializing the IBPMU37211.2 Using the IBPMU37311.2.1 Monitored Events South AHB and North AHB37511.2.2 Monitored SDRAM Events37711.2.3 Cycle Count37711.3 Register Descriptions37811.3.1 Event Select Register37811.3.2 PMU Status Register (PSR)38111.3.3 Programmable Event Counters (PEC1)38111.3.4 Programmable Event Counters (PEC2)38211.3.5 Programmable Event Counters (PEC3)38211.3.6 Programmable Event Counters (PEC4)38211.3.7 Programmable Event Counters (PEC5)38311.3.8 Programmable Event Counters (PEC6)38311.3.9 Programmable Event Counters (PEC7)38411.3.10 Previous Master/Slave Register (PSMR)38412.0 General Purpose Input/Output (GPIO)38612.1 Using GPIO as Inputs/Outputs38612.2 Using GPIO as Interrupt Inputs38712.3 Using GPIO 14 and GPIO 15 as Clocks38912.4 Register Description39112.4.1 GPIO Output Register39112.4.2 GPIO Output Enable Register39212.4.3 GPIO Input Register39212.4.4 GPIO Interrupt Status Register39312.4.5 GP Interrupt Type Register 139312.4.6 GPIO Interrupt Type Register 239412.4.7 GPIO Clock Register39513.0 Interrupt Controller39813.1 Interrupt Priority39813.2 Assigning FIQ or IRQ Interrupts39913.3 Enabling and Disabling Interrupts39913.4 Reading Interrupt Status40013.5 Interrupt Controller Register Description40113.5.1 Interrupt Status Register40213.5.2 Interrupt-Enable Register40413.5.3 Interrupt Select Register40413.5.4 IRQ Status Register40413.5.5 FIQ Status Register40413.5.6 Interrupt Priority Register40513.5.7 IRQ Highest-Priority Register40513.5.8 FIQ Highest-Priority Register40614.0 Timers40814.1 Watch-Dog Timer40814.2 Time-Stamp Timer40914.3 General-Purpose Timers40914.4 Timer Register Definition41114.4.1 Time-Stamp Timer41114.4.2 General-Purpose Timer 041114.4.3 General-Purpose Timer 0 Reload41214.4.4 General-Purpose Timer 141214.4.5 General-Purpose Timer 1 Reload41314.4.6 Watch-Dog Timer41314.4.7 Watch-Dog Enable Register41414.4.8 Watch-Dog Key Register41414.4.9 Timer Status41515.0 Ethernet MAC A41615.1 Ethernet Coprocessor41715.1.1 Ethernet Coprocessor APB Interface41815.1.2 Ethernet Coprocessor NPE Interface41815.1.3 Ethernet Coprocessor MDIO Interface41815.1.4 Transmitting Ethernet Frames with MII Interfaces42015.1.5 Receiving Ethernet Frames with MII Interfaces42315.1.6 General Ethernet Coprocessor Configuration42515.2 Register Descriptions42715.2.1 Transmit Control 142815.2.2 Transmit Control 242915.2.3 Receive Control 142915.2.4 Receive Control 243015.2.5 Random Seed43015.2.6 Threshold For Partially Empty43115.2.7 Threshold For Partially Full43115.2.8 Buffer Size For Transmit43115.2.9 Transmit Deferral Parameters43215.2.10 Receive Deferral Parameters43215.2.11 Transmit Two Part Deferral Parameters 143315.2.12 Transmit Two Part Deferral Parameters 243315.2.13 Slot Time43315.2.14 MDIO Commands Registers43415.2.15 MDIO Command 143415.2.16 MDIO Command 243415.2.17 MDIO Command 343515.2.18 MDIO Command 443515.2.19 MDIO Status Registers43515.2.20 MDIO Status 143615.2.21 MDIO Status 243615.2.22 MDIO Status 343615.2.23 MDIO Status 443615.2.24 Address Mask Registers43715.2.25 Address Mask 143715.2.26 Address Mask 243815.2.27 Address Mask 343815.2.28 Address Mask 443815.2.29 Address Mask 543815.2.30 Address Mask 643915.2.31 Address Registers43915.2.32 Address 144015.2.33 Address 244015.2.34 Address 344015.2.35 Address 444015.2.36 Address 544115.2.37 Address 644115.2.38 Threshold for Internal Clock44215.2.39 Unicast Address Registers44215.2.40 Unicast Address 144315.2.41 Unicast Address 244315.2.42 Unicast Address 344315.2.43 Unicast Address 444315.2.44 Unicast Address 544415.2.45 Unicast Address 644415.2.46 Core Control44416.0 Ethernet MAC B44617.0 High-Speed Serial Interfaces44817.1 High-Speed Serial Interface Receive Operation44817.2 High-Speed Serial Interface Transmit Operation44917.3 Configuration of the High-Speed Serial Interface45017.4 Obtaining High-Speed, Serial Synchronization45317.5 HSS Registers and Clock Configuration45417.5.1 HSS Clock and Jitter45517.5.2 Overview of HSS Clock Configuration45517.6 HSS Supported Framing Protocols45717.6.1 T145717.6.2 E145917.6.3 MVIP46017.6.3.1 MVIP using 2.048Mbps Backplane46117.6.3.2 MVIP Using 4.096-Mbps Backplane46317.6.3.3 MVIP Using 8.192-Mbps Backplane46418.0 Universal Serial Bus (USB) v1.1 Device Controller46818.1 USB Overview46818.2 Device Configuration46918.3 USB Operation47018.3.1 Signalling Levels47018.3.2 Bit Encoding47118.3.3 Field Formats47218.3.4 Packet Formats47418.3.4.1 Token Packet Type47418.3.4.2 Start-of-Frame Packet Type47418.3.4.3 Data Packet Type47418.3.4.4 Handshake Packet Type47518.3.5 Transaction Formats47518.3.5.1 Bulk Transaction Type47518.3.5.2 Isochronous Transaction Type47618.3.5.3 Control Transaction Type47618.3.5.4 Interrupt Transaction Type47718.3.6 UDC Device Requests47718.3.7 UDC Configuration47818.4 UDC Hardware Connections47918.4.1 Self-Powered Device47918.4.2 Bus-Powered Devices47918.5 Register Descriptions47918.5.1 UDC Control Register (UDCCR)48118.5.1.1 UDC Enable48118.5.1.2 UDC Active48118.5.1.3 UDC Resume (RSM)48118.5.1.4 Resume Interrupt Request (RESIR)48218.5.1.5 Suspend Interrupt Request (SUSIR)48218.5.1.6 Suspend/Resume Interrupt Mask (SRM)48218.5.1.7 Reset Interrupt Request (RSTIR)48218.5.1.8 Reset Interrupt Mask (REM)48218.5.2 UDC Endpoint 0 Control/Status Register (UDCCS0)48318.5.2.1 OUT Packet Ready (OPR)48318.5.2.2 IN Packet Ready (IPR)48318.5.2.3 Flush Tx FIFO (FTF)48418.5.2.4 Device Remote Wake-Up Feature (DRWF)48418.5.2.5 Sent Stall (SST)48418.5.2.6 Force Stall (FST)48418.5.2.7 Receive FIFO Not Empty (RNE)48418.5.2.8 Setup Active (SA)48418.5.3 UDC Endpoint 1 Control/Status Register (UDCCS1)48518.5.3.1 Transmit FIFO Service (TFS)48518.5.3.2 Transmit Packet Complete (TPC)48618.5.3.3 Flush Tx FIFO (FTF)48618.5.3.4 Transmit Underrun (TUR)48618.5.3.5 Sent STALL (SST)48618.5.3.6 Force STALL (FST)48618.5.3.7 Bit 6 Reserved48718.5.3.8 Transmit Short Packet (TSP)48718.5.4 UDC Endpoint 2 Control/Status Register (UDCCS2)48718.5.4.1 Receive FIFO Service (RFS)48818.5.4.2 Receive Packet Complete (RPC)48818.5.4.3 Bit 2 Reserved48818.5.4.4 Bit 2 Reserved48818.5.4.5 Sent Stall (SST)48818.5.4.6 Force Stall (FST)48818.5.4.7 Receive FIFO Not Empty (RNE)48818.5.4.8 Receive Short Packet (RSP)48918.5.5 UDC Endpoint 3 Control/Status Register (UDCCS3)49018.5.5.1 Transmit FIFO Service (TFS)49018.5.5.2 Transmit Packet Complete (TPC)49018.5.5.3 Flush Tx FIFO (FTF)49018.5.5.4 Transmit Underrun (TUR)49018.5.5.5 Bit 4 Reserved49018.5.5.6 Bit 5 Reserved49018.5.5.7 Bit 6 Reserved49018.5.5.8 Transmit Short Packet (TSP)49118.5.6 UDC Endpoint 4 Control/Status Register (UDCCS4)49118.5.6.1 Receive FIFO Service (RFS)49118.5.6.2 Receive Packet Complete (RPC)49218.5.6.3 Receive Overflow (ROF)49218.5.6.4 Bit 3 Reserved49218.5.6.5 Bit 4 Reserved49218.5.6.6 Bit 5 Reserved49218.5.6.7 Receive FIFO Not Empty (RNE)49218.5.6.8 Receive Short Packet (RSP)49218.5.7 UDC Endpoint 5 Control/Status Register (UDCCS5)49318.5.7.1 Transmit FIFO Service (TFS)49318.5.7.2 Transmit Packet Complete (TPC)49318.5.7.3 Flush Tx FIFO (FTF)49418.5.7.4 Transmit Underrun (TUR)49418.5.7.5 Sent STALL (SST)49418.5.7.6 Force STALL (FST)49418.5.7.7 Bit 6 Reserved49418.5.7.8 Transmit Short Packet (TSP)49518.5.8 UDC Endpoint 6 Control/Status Register49518.5.8.1 Transmit FIFO Service (TFS)49618.5.8.2 Transmit Packet Complete (TPC)49618.5.8.3 Flush Tx FIFO (FTF)49618.5.8.4 Transmit Underrun (TUR)49618.5.8.5 Sent STALL (SST)49618.5.8.6 Force STALL (FST)49618.5.8.7 Bit 6 Reserved49718.5.8.8 Transmit Short Packet (TSP)49718.5.9 UDC Endpoint 7 Control/Status Register (UDCCS7)49818.5.9.1 Receive FIFO Service (RFS)49818.5.9.2 Receive Packet Complete (RPC)49818.5.9.3 Bit 2 Reserved49818.5.9.4 Bit 3 Reserved49818.5.9.5 Sent Stall (SST)49818.5.9.6 Force Stall (FST)49818.5.9.7 Receive FIFO Not Empty (RNE)49918.5.9.8 Receive Short Packet (RSP)49918.5.10 UDC Endpoint 8 Control/Status Register (UDCCS8)50018.5.10.1 Transmit FIFO Service (TFS)50018.5.10.2 Transmit Packet Complete (TPC)50018.5.10.3 Flush Tx FIFO (FTF)50018.5.10.4 Transmit Underrun (TUR)50018.5.10.5 Bit 4 Reserved50018.5.10.6 Bit 5 Reserved50118.5.10.7 Bit 6 Reserved50118.5.10.8 Transmit Short Packet (TSP)50118.5.11 UDC Endpoint 9 Control/Status Register (UDCCS9)50218.5.11.1 Receive FIFO Service (RFS)50218.5.11.2 Receive Packet Complete (RPC)50218.5.11.3 Receive Overflow (ROF)50218.5.11.4 Bit 3 Reserved50218.5.11.5 Bit 4 Reserved50218.5.11.6 Bit 5 Reserved50218.5.11.7 Receive FIFO Not Empty (RNE)50218.5.11.8 Receive Short Packet (RSP)50218.5.12 UDC Endpoint 10 Control/Status Register (UDCCS10)50318.5.12.1 Transmit FIFO Service (TFS)50318.5.12.2 Transmit Packet Complete (TPC)50318.5.12.3 Flush Tx FIFO (FTF)50418.5.12.4 Transmit Underrun (TUR)50418.5.12.5 Sent STALL (SST)50418.5.12.6 Force STALL (FST)50418.5.12.7 Bit 6 Reserved50418.5.12.8 Transmit Short Packet (TSP)50518.5.13 UDC Endpoint 11 Control/Status Register (UDCCS11)50518.5.13.1 Transmit FIFO Service (TFS)50618.5.13.2 Transmit Packet Complete (TPC)50618.5.13.3 Flush Tx FIFO (FTF)50618.5.13.4 Transmit Underrun (TUR)50618.5.13.5 Sent STALL (SST)50618.5.13.6 Force STALL (FST)50618.5.13.7 Bit 6 Reserved50718.5.13.8 Transmit Short Packet (TSP)50718.5.14 UDC Endpoint 12 Control/Status Register (UDCCS12)50818.5.14.1 Receive FIFO Service (RFS)50818.5.14.2 Receive Packet Complete (RPC)50818.5.14.3 Bit 2 Reserved50818.5.14.4 Bit 3 Reserved50818.5.14.5 Sent Stall (SST)50818.5.14.6 Force Stall (FST)50918.5.14.7 Receive FIFO Not Empty (RNE)50918.5.14.8 Receive Short Packet (RSP)50918.5.15 UDC Endpoint 13 Control/Status Register (UDCCS13)51018.5.15.1 Transmit FIFO Service (TFS)51018.5.15.2 Transmit Packet Complete (TPC)51018.5.15.3 Flush Tx FIFO (FTF)51018.5.15.4 Transmit Underrun (TUR)51118.5.15.5 Bit 4 Reserved51118.5.15.6 Bit 5 Reserved51118.5.15.7 Bit 6 Reserved51118.5.15.8 Transmit Short Packet (TSP)51118.5.16 UDC Endpoint 14 Control/Status Register (UDCCS14)51218.5.16.1 Receive FIFO Service (RFS)51218.5.16.2 Receive Packet Complete (RPC)51218.5.16.3 Receive Overflow (ROF)51218.5.16.4 Bit 3 Reserved51218.5.16.5 Bit 4 Reserved51218.5.16.6 Bit 5 Reserved51218.5.16.7 Receive FIFO Not Empty (RNE)51318.5.16.8 Receive Short Packet (RSP)51318.5.17 UDC Endpoint 15 Control/Status Register (UDCCS15)51418.5.17.1 Transmit FIFO Service (TFS)51418.5.17.2 Transmit Packet Complete (TPC)51418.5.17.3 Flush Tx FIFO (FTF)51418.5.17.4 Transmit Underrun (TUR)51418.5.17.5 Sent STALL (SST)51518.5.17.6 Force STALL (FST)51518.5.17.7 Bit 6 Reserved51518.5.17.8 Transmit Short Packet (TSP)51518.5.18 UDC Interrupt Control Register 0 (UICR0)51618.5.18.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 751618.5.19 UDC Interrupt Control Register 1 (UICR1)51718.5.19.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15.51718.5.20 UDC Status/Interrupt Register 0 (UISR0)51818.5.20.1 Endpoint 0 Interrupt Request (IR0)51918.5.20.2 Endpoint 1 Interrupt Request (IR1)51918.5.20.3 Endpoint 2 Interrupt Request (IR2)51918.5.20.4 Endpoint 3 Interrupt Request (IR3)51918.5.20.5 Endpoint 4 Interrupt Request (IR4)51918.5.20.6 Endpoint 5 Interrupt Request (IR5)51918.5.20.7 Endpoint 6 Interrupt Request (IR6)52018.5.20.8 Endpoint 7 Interrupt Request (IR7)52018.5.21 UDC Status/Interrupt Register 1 (USIR1)52118.5.21.1 Endpoint 8 Interrupt Request (IR8)52118.5.21.2 Endpoint 9 Interrupt Request (IR9)52118.5.21.3 Endpoint 10 Interrupt Request (IR10)52118.5.21.4 Endpoint 11 Interrupt Request (IR11)52118.5.21.5 Endpoint 12 Interrupt Request (IR12)52118.5.21.6 Endpoint 13 Interrupt Request (IR13)52118.5.21.7 Endpoint 14 Interrupt Request (IR14)52118.5.21.8 Endpoint 15 Interrupt Request (IR15)52218.5.22 UDC Frame Number High Register (UFNHR)52218.5.22.1 UDC Frame Number MSB (FNMSB)52218.5.22.2 Isochronous Packet Error Endpoint 4 (IPE4)52318.5.22.3 Isochronous Packet Error Endpoint 9 (IPE9)52318.5.22.4 Isochronous Packet Error Endpoint 14 (IPE14)52318.5.22.5 Start of Frame Interrupt Mask (SIM)52318.5.22.6 Start of Frame Interrupt Request (SIR)52318.5.23 UDC Frame Number Low Register (UFNLR)52418.5.24 UDC Byte Count Register 2 (UBCR2)52418.5.24.1 Endpoint 2 Byte Count (BC[7:0])52518.5.25 UDC Byte Count Register 4 (UBCR4)52518.5.25.1 Endpoint 4 Byte Count (BC[7:0])52518.5.26 UDC Byte Count Register 7 (UBCR7)52618.5.26.1 Endpoint 7 Byte Count (BC[7:0])52618.5.27 UDC Byte Count Register 9 (UBCR9)52618.5.27.1 Endpoint 9 Byte Count (BC[7:0])52618.5.28 UDC Byte Count Register 12 (UBCR12)52718.5.28.1 Endpoint 12 Byte Count (BC[7:0])52718.5.29 UDC Byte Count Register 14 (UBCR14)52818.5.29.1 Endpoint 14 Byte Count (BC[7:0])52818.5.30 UDC Endpoint 0 Data Register (UDDR0)52818.5.31 UDC Data Register 1 (UDDR1)52918.5.32 UDC Data Register 2 (UDDR2)52918.5.33 UDC Data Register 3 (UDDR3)53018.5.34 UDC Data Register 4 (UDDR4)53118.5.35 UDC Data Register 5 (UDDR5)53118.5.36 UDC Data Register 6 (UDDR6)53218.5.37 UDC Data Register 7 (UDDR7)53218.5.38 UDC Data Register 8 (UDDR8)53318.5.39 UDC Data Register 9 (UDDR9)53318.5.40 UDC Data Register 10 (UDDR10)53418.5.41 UDC Data Register 1153518.5.42 UDC Data Register 12 (UDDR12)53518.5.43 UDC Data Register 13 (UDDR13)53618.5.44 UDC Data Register 14 (UDDR14)53618.5.45 UDC Data Register 15 (UDDR15)53719.0 UTOPIA Level-253819.1 UTOPIA Transmit Module54019.2 UTOPIA Receive Module54319.3 UTOPIA-2 Coprocessor / NPE Coprocessor: Bus Interface54519.4 MPHY Polling Routines54619.5 UTOPIA Level-2 Clocks54620.0 JTAG Interface54820.1 TAP Controller54820.1.1 Test-Logic-Reset State54920.1.2 Run-Test/Idle State55020.1.3 Select-DR-Scan State55020.1.4 Capture-DR State55020.1.5 Shift-DR State55020.1.6 Exit1-DR State55120.1.7 Pause-DR State55120.1.8 Exit2-DR State55120.1.9 Update-DR State55120.1.10 Select-IR-Scan State55220.1.11 Capture-IR State55220.1.12 Shift-IR State55220.1.13 Exit1-IR State55220.1.14 Pause-IR State55220.1.15 Exit2-IR State55320.1.16 Update-IR State55320.2 JTAG Instructions55320.3 Data Registers55420.3.1 Boundary Scan Register55520.3.2 Instruction Register55520.3.3 JTAG Device ID Register55521.0 AHB Queue Manager (AQM)55621.1 Overview55621.2 Feature List55621.3 Functional Description55721.4 AHB Interface55821.4.1 Queue Control55921.4.2 Queue Status56021.4.2.1 Status Update56021.4.2.2 Flag Bus56121.4.2.3 Status Interrupts56221.5 Register Descriptions56221.5.1 Queue Access Word Registers 0 - 6356221.5.2 Queues 0-31 Status Register 0 - 356321.5.3 Underflow/Overflow Status Register 0 - 156321.5.4 Queues 32-63 Nearly Empty Status Register56421.5.5 Queues 32-63 Full Status Register56421.5.6 Interrupt 0 Status Flag Source Select Register 0 - 356521.5.7 Queue Interrupt Enable Register 0 - 156621.5.8 Queue Interrupt Register 0 - 156621.5.9 Queue Configuration Words 0 - 63566文件大小： 4.3 MB页数： 568Language: English打开用户手册
