Intel IXC1100 用户手册

Intel

®

 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

September 2006

DM

Order Number: 252480-006US

301

the T3 – Strobe Timing parameter to be two clock cycles in length ensures that any 

data sent to the DSP is captured regardless of when the EX_RDY signal is asserted by 

the DSP.

The Hold Phase of an expansion-bus access is provided to allow a hold time for data to 

remain valid after the data strobe has transitioned to an invalid state. During a write 

access, the Hold Phase provides hold time for data written to an external device on the 

expansion bus, after the strobe pulse has completed. 

During a read access, the Hold Phase allows an external device time to release the bus 

after driving data back to the controller. The Hold Phase may be extended one to three 

clock cycles, using bits 21:20 of the Timing and Control (EXP_TIMING_CS) Register, T4 

– Hold Timing parameter. In HPI mode of operation, the Hold Phase is defined the same 

as described for the Intel and Motorola* modes of operation.

After the address and chip select is de-asserted, the Expansion Bus Controller can be 

programmed to wait a number of clocks before starting the next Expansion Bus access. 

This action is referred to as the Recovery Phase. The Recovery Phase is may be 

extended one to 15 clock cycles using bits 19:16 of the Timing and Control 

(EXP_TIMING_CS) Register, T5 – Recovery Timing parameter. In HPI mode of 

operation, the Recovery Phase is defined the same as described for the Intel and 

Motorola modes of operation.

The EX_IOWAIT_N signal is available to be shared by devices attached to chip selects 0 

through 7, when configured in Intel or Motorola modes of operation. The main purpose 

of this signal is to properly communicate with slower devices requiring more time to 

respond during data access. During idle cycles, the board is responsible for ensuring 

that EX_IOWAIT_N is pulled-up. The Expansion bus controller will always ignore 

EX_IOWAIT_N for synchronous Intel mode writes.

As shown in 

, a normal phase transaction is initiated during the T1 (Address 

Timing) period, in which the processor drives the address lines with an address that is 

decoded by the peripheral being accessed.

The next segment of the transaction is the T2 (Chip Select Timing) period, in which the 

processor asserts Chip Select and the Address signals have reached a stable state. 

EX_IOWAIT_N must be asserted during the T2 period. If not asserted at this time, the 

processor ignores EX_IOWAIT_N and treats it as it never occurred. If EX_IOWAIT_N is 

asserted during T2, the processor expects the signal to be deasserted during the T3 

(Strobe Timing) period. 

T3 can be programmed from 0 to F, where the value indicates the number of cycles that 

the processor waits for EX_IOWAIT_N to be deasserted. The counter starts at the rising 

edge of the clock when EX_RD_N or EX_WR_N is asserted. The following rules describe 

processor operation during T3:

• If EX_IOWAIT_N is deasserted at least two clock cycles before the T3 counter 

expires, then the processor deasserts EX_RD_N/EX_WR_N at the end of the 

number of cycles programmed in T3.

• If EX_IOWAIT_N is deasserted after T3 counter has expired, it will take 2 more 

clock cycles before the processor deasserts the EX_RD_N/EX_WR_N signal. 

• If EX_IOWAIT_N is not deasserted before the T3 counter expires, then EX_RD_N/

EX_WR_N will continue to be asserted for as long as EX_IOWAIT_N continues to be 

asserted, plus 2 more clock cycles.