用户手册 (CM80616005010AA)目录1 Introduction171.1 Register Terminology172 Configuration Process and Registers192.1 Platform Configuration Structure192.1.1 Processor Integrated I/O (IIO) Devices (PCI Bus 0)192.1.2 Processor Uncore Devices (PCI Bus — FFh)202.2 Configuration Mechanisms212.2.1 Standard PCI Express* Configuration Mechanism212.2.2 PCI Express* Configuration Mechanism212.3 Routing Configuration Accesses232.3.1 Internal Device Configuration Accesses242.3.2 Bridge-Related Configuration Accesses242.4 Processor Register Introduction252.5 I/O Mapped Registers263 Processor Integrated I/O (IIO) Configuration Registers273.1 Processor IIO Devices (PCI Bus 0)273.2 Device Mapping283.2.1 Unimplemented Devices/Functions and Registers283.3 PCI Express*/DMI Configuration Registers283.3.1 Other Register Notes283.3.2 Configuration Register Map293.3.3 Standard PCI Configuration Space (0h to 3Fh) — Type 0/1 Common Configuration Space353.3.4 Device-Specific PCI Configuration Space — 40h to FFh513.3.5 PCIe/DMI Extended Configuration Space793.3.6 DMI Root Complex Register Block843.4 Integrated I/O Core Registers (Device 8, Function 0-3)923.4.1 Configuration Register Map (Device 8, Function 0-3)923.4.2 Standard PCI Configuration Registers983.4.3 Common Extended Configuration Space Registers1043.4.4 Intel® VT-d, Address Mapping, System Management Registers (Device 8, Function 0)1103.4.5 Semaphore and ScratchPad Registers (Dev:8, F:1)1273.4.6 System Control/Status Registers (Device 8, Function 2)1333.4.7 Miscellaneous Registers (Dev:8, F:3)1343.5 Intel® VT-d Memory Mapped Registers1363.5.1 Intel® VT-d Configuration Register Space (MMIO)1373.5.2 Register Description1403.6 Intel® Trusted Execution Technology (Intel® TXT) Register Map1563.6.1 Intel® TXT Space Registers1613.7 Intel® QuickPath Interconnect Device/Functions1753.7.1 Intel® QuickPath Interconnect Link Layer Registers1763.7.2 Intel® QuickPath Interconnect Routing & Protocol Layer Registers1794 Processor Uncore Configuration Registers1834.1 Processor Uncore Configuration Structure (PCI Bus — FFh)1834.2 Device Mapping1844.3 Detailed Configuration Space Maps1854.4 PCI Standard Registers2014.4.1 VID—Vendor Identification Register2014.4.2 DID—Device Identification Register2014.4.3 RID—Revision Identification Register2024.4.4 CCR—Class Code Register2044.4.5 HDR—Header Type Register2054.4.6 SVID—Subsystem Vendor Identification Register2054.4.7 SID—Subsystem Identity2064.4.8 PCICMD—Command Register2074.4.9 PCISTS—PCI Status Register2084.5 SAD—System Address Decoder Registers2094.5.1 SAD_PAM01232094.5.2 SAD_PAM4562114.5.3 SAD_HEN2124.5.4 SAD_SMRAM2124.5.5 SAD_PCIEXBAR2134.5.6 SAD_TPCIEXBAR2134.5.7 SAD_MCSEG_BASE2144.5.8 SAD_MCSEG_MASK2144.5.9 SAD_MESEG_BASE2154.5.10 SAD_MESEG_MASK2154.5.11 SAD_DRAM_RULE_0; SAD_DRAM_RULE_1 SAD_DRAM_RULE_2; SAD_DRAM_RULE_3 SAD_DRAM_RULE_4; SAD_DRAM_RULE_5 SAD_DRAM_RULE_6; SAD_DRAM_RULE_72164.5.12 SAD_INTERLEAVE_LIST_0; SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_2; SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4; SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6; SAD_INTERLEAVE_LIST_72174.6 Intel® QuickPath Interconnect Link Registers2184.6.1 QPI_QPILCL_L02184.7 Integrated Memory Controller Control Registers2204.7.1 MC_CONTROL2204.7.2 MC_SMI_DIMM_ERROR_STATUS2214.7.3 MC_SMI_CNTRL2214.7.4 MC_STATUS2224.7.5 MC_RESET_CONTROL2224.7.6 MC_CHANNEL_MAPPER2234.7.7 MC_MAX_DOD2234.7.8 MC_CFG_LOCK2244.7.9 MC_RD_CRDT_INIT2254.7.10 MC_CRDT_WR_THLD2264.8 TAD—Target Address Decoder Registers2274.8.1 TAD_DRAM_RULE_0; TAD_DRAM_RULE_1 TAD_DRAM_RULE_2; TAD_DRAM_RULE_3 TAD_DRAM_RULE_4; TAD_DRAM_RULE_5 TAD_DRAM_RULE_6; TAD_DRAM_RULE_72274.8.2 TAD_INTERLEAVE_LIST_0; TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2; TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4; TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6; TAD_INTERLEAVE_LIST_72284.9 Integrated Memory Controller Test Registers2294.9.1 MC_COR_ECC_CNT_0 MC_COR_ECC_CNT_1 MC_COR_ECC_CNT_2 MC_COR_ECC_CNT_32294.9.2 Integrated Memory Controller Padscan2294.9.3 MC_DIMM_CLK_RATIO_STATUS2324.9.4 MC_DIMM_CLK_RATIO2334.9.5 MC_TEST_LTRCON2334.9.6 MC_TEST_PH_CTR2344.9.7 MC_TEST_PH_PIS2344.9.8 MC_TEST_PAT_GCTR2354.9.9 MC_TEST_PAT_BA2364.9.10 MC_TEST_PAT_IS2364.9.11 MC_TEST_PAT_DCD2364.9.12 MC_TEST_EP_SCCTL2374.9.13 MC_TEST_EP_SCD2374.10 Integrated Memory Controller Channel Control Registers2384.10.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD2384.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD2394.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS2404.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS2414.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD2424.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT2434.10.7 MC_CHANNEL_0_MRS_VALUE_0_1 MC_CHANNEL_1_MRS_VALUE_0_12434.10.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_22444.10.9 MC_CHANNEL_0_RANK_PRESENT MC_CHANNEL_1_RANK_PRESENT2454.10.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A2464.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B2484.10.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING2494.10.13 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING2494.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING2504.10.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING2514.10.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS2514.10.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS12524.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS22534.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD2534.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD2544.10.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR2544.10.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR2544.10.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS2554.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS2564.10.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS2564.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS2574.10.27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS2584.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS2584.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS2594.10.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_1_ROUND_TRIP_LATENCY2594.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS12604.10.32 MC_CHANNEL_0_PAGETABLE_PARAMS2 MC_CHANNEL_1_PAGETABLE_PARAMS22604.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH12614.10.34 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 MC_TX_BG_CMD_OFFSET_SETTINGS_CH12614.10.35 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0 MC_TX_BG_DATA_OFFSET_SETTINGS_CH12614.10.36 MC_CHANNEL_0_ADDR_MATCH MC_CHANNEL_1_ADDR_MATCH2624.10.37 MC_CHANNEL_0_ECC_ERROR_MASK MC_CHANNEL_1_ECC_ERROR_MASK2634.10.38 MC_CHANNEL_0_ECC_ERROR_INJECT MC_CHANNEL_1_ECC_ERROR_INJECT2634.10.39 Error Injection Implementation2634.11 Integrated Memory Controller Channel Address Registers2644.11.1 MC_DOD_CH0_0 MC_DOD_CH0_12644.11.2 MC_DOD_CH1_0 MC_DOD_CH1_12654.11.3 MC_SAG_CH0_0; MC_SAG_CH0_1; MC_SAG_CH0_2; MC_SAG_CH0_3; MC_SAG_CH0_4; MC_SAG_CH0_5; MC_SAG_CH0_6; MC_SAG_CH0_72664.11.4 MC_SAG_CH1_0; MC_SAG_CH1_1; MC_SAG_CH1_2; MC_SAG_CH1_3; MC_SAG_CH1_4; MC_SAG_CH1_5; MC_SAG_CH1_6; MC_SAG_CH1_72674.12 Integrated Memory Controller Channel Rank Registers2684.12.1 MC_RIR_LIMIT_CH0_0; MC_RIR_LIMIT_CH0_1; MC_RIR_LIMIT_CH0_2; MC_RIR_LIMIT_CH0_3; MC_RIR_LIMIT_CH0_4; MC_RIR_LIMIT_CH0_5; MC_RIR_LIMIT_CH0_6; MC_RIR_LIMIT_CH0_72684.12.2 MC_RIR_LIMIT_CH1_0; MC_RIR_LIMIT_CH1_1; MC_RIR_LIMIT_CH1_2; MC_RIR_LIMIT_CH1_3; MC_RIR_LIMIT_CH1_4; MC_RIR_LIMIT_CH1_5; MC_RIR_LIMIT_CH1_6; MC_RIR_LIMIT_CH1_72684.12.3 MC_RIR_WAY_CH0_0; MC_RIR_WAY_CH0_1; MC_RIR_WAY_CH0_2; MC_RIR_WAY_CH0_3; MC_RIR_WAY_CH0_4; MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6; MC_RIR_WAY_CH0_7 MC_RIR_WAY_CH0_8; MC_RIR_WAY_CH0_9 MC_RIR_WAY_CH0_10; MC_RIR_WAY_CH0_11 MC_RIR_WAY_CH0_12; MC_RIR_WAY...2694.12.4 MC_RIR_WAY_CH1_0; MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2; MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4; MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6; MC_RIR_WAY_CH1_7 MC_RIR_WAY_CH1_8; MC_RIR_WAY_CH1_9 MC_RIR_WAY_CH1_10; MC_RIR_WAY_CH1_11 MC_RIR_WAY_CH1_12; MC_RIR_WAY_C...2704.13 Memory Thermal Control2714.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL12714.13.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS12714.13.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE12724.13.4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A12724.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B12734.13.6 MC_COOLING_COEF0 MC_COOLING_COEF12734.13.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP12744.13.8 MC_THROTTLE_OFFSET0 MC_THROTTLE_OFFSET12744.13.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP12754.13.10 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_COMMAND12754.13.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS12765 System Address Map2775.1 Introduction2775.2 Memory Address Space2785.2.1 System Address Map2795.2.2 System DRAM Memory Regions2805.2.3 VGA/SMM and Legacy C/D/E/F Regions2815.2.4 Address Region between 1 MB and TOLM2825.2.5 Address Region from TOLM to 4 GB2835.2.6 Address Regions above 4 GB2865.2.7 Protected System DRAM Regions2875.3 IO Address Space2875.3.1 VGA I/O Addresses2875.3.2 ISA Addresses2885.3.3 CFC/CF8 Addresses2885.3.4 PCIe Device I/O Addresses2885.4 Configuration/CSR Space2885.4.1 PCIe Configuration Space2885.5 System Management Mode (SMM)2895.5.1 SMM Space Definition2895.5.2 SMM Space Restrictions2905.5.3 SMM Space Combinations2905.5.4 SMM Control Combinations2915.5.5 SMM Space Decode and Transaction Handling2915.5.6 Processor WB Transaction to an Enabled SMM Address Space2915.5.7 SMM Access Through GTT TLB2915.6 Memory Shadowing2925.7 IIO Address Map Notes2925.7.1 Memory Recovery2925.7.2 Non-Coherent Address Space2925.8 IIO Address Decoding2935.8.1 Outbound Address Decoding2935.8.2 Inbound Address Decoding2975.8.3 Intel® VT-d Address Map Implications302文件大小： 1.7 MB页数： 302Language: English打开用户手册
