数据表 (CH80566EE014DT)目录Contents3Figures4Tables4Revision History51 Introduction71.1 Abstract71.2 Major Features71.3 Terminology91.4 References112 Low Power Features132.1 Clock Control and Low-Power States132.1.1 Package/Core Low-Power State Descriptions152.2 Dynamic Cache Sizing222.3 Enhanced Intel SpeedStep® Technology232.4 Enhanced Low-Power States242.5 FSB Low Power Enhancements252.5.1 CMOS Front Side Bus252.6 Intel® Burst Performance Technology (Intel® BPT)263 Electrical Specifications273.1 FSB, GTLREF, and CMREF273.2 Power and Ground Pins273.3 Decoupling Guidelines283.3.1 VCC Decoupling283.3.2 FSB AGTL+ Decoupling283.4 FSB Clock (BCLK[1:0]) and Processor Clocking283.5 Voltage Identification and Power Sequencing283.6 Catastrophic Thermal Protection313.7 Reserved and Unused Pins313.8 FSB Frequency Select Signals (BSEL[2:0])313.9 FSB Signal Groups313.10 CMOS Asynchronous Signals333.11 Maximum Ratings333.12 Processor DC Specifications343.13 AGTL+ FSB Specifications454 Package Mechanical Specifications and Pin Information474.1 Package Mechanical Specifications474.1.1 Processor Package Weight474.2 Processor Pinout Assignment494.3 Signal Description565 Thermal Specifications and Design Considerations655.1 Thermal Specifications685.1.1 Thermal Diode685.1.2 Intel® Thermal Monitor705.1.3 Digital Thermal Sensor725.1.4 Out of Specification Detection725.1.5 PROCHOT# Signal Pin72文件大小: 1.5 MB页数: 73Language: English打开用户手册