用户手册 — Intel Z520PT

目录

• Contents

  3
• Figures

  4
• Tables

  4
  • Revision History

    5
• 1 Introduction

  7
  • 1.1 Abstract

    7
  • 1.2 Major Features

    7
  • 1.3 Terminology

    9
  • 1.4 References

    11
• 2 Low Power Features

  13
  • 2.1 Clock Control and Low-Power States

    13
    • 2.1.1 Package/Core Low-Power State Descriptions

      15
  • 2.2 Dynamic Cache Sizing

    22
  • 2.3 Enhanced Intel SpeedStep® Technology

    23
  • 2.4 Enhanced Low-Power States

    24
  • 2.5 FSB Low Power Enhancements

    25
    • 2.5.1 CMOS Front Side Bus

      25
  • 2.6 Intel® Burst Performance Technology (Intel® BPT)

    26
• 3 Electrical Specifications

  27
  • 3.1 FSB, GTLREF, and CMREF

    27
  • 3.2 Power and Ground Pins

    27
  • 3.3 Decoupling Guidelines

    28
    • 3.3.1 VCC Decoupling

      28
    • 3.3.2 FSB AGTL+ Decoupling

      28
  • 3.4 FSB Clock (BCLK[1:0]) and Processor Clocking

    28
  • 3.5 Voltage Identification and Power Sequencing

    28
  • 3.6 Catastrophic Thermal Protection

    31
  • 3.7 Reserved and Unused Pins

    31
  • 3.8 FSB Frequency Select Signals (BSEL[2:0])

    31
  • 3.9 FSB Signal Groups

    31
  • 3.10 CMOS Asynchronous Signals

    33
  • 3.11 Maximum Ratings

    33
  • 3.12 Processor DC Specifications

    34
  • 3.13 AGTL+ FSB Specifications

    45
• 4 Package Mechanical Specifications and Pin Information

  47
  • 4.1 Package Mechanical Specifications

    47
    • 4.1.1 Processor Package Weight

      47
  • 4.2 Processor Pinout Assignment

    49
  • 4.3 Signal Description

    56
• 5 Thermal Specifications and Design Considerations

  65
  • 5.1 Thermal Specifications

    68
    • 5.1.1 Thermal Diode

      68
    • 5.1.2 Intel® Thermal Monitor

      70
    • 5.1.3 Digital Thermal Sensor

      72
    • 5.1.4 Out of Specification Detection

      72
    • 5.1.5 PROCHOT# Signal Pin

      72