用户手册 — JL MARINE SYSTEMS INC. EA041

目录

• 1 Description

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• 2 RoHS compliance

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• 3 Applications

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• 4 Software architecture

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  • 4.1 Lower layer stack

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  • 4.2 Upper layer stack: Amp'ed UP

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  • 4.3 AT command set: abSerial

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  • 4.4 Bluetooth firmware implementation

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    • Figure 1. FW architecture

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• 5 Hardware specifications

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  • 5.1 Recommended operating conditions

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    • Table 1. Recommended operating conditions

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  • 5.2 Absolute maximum ratings

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    • Table 2. Absolute maximum ratings

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  • 5.3 High speed CPU mode current consumption

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    • Table 3. High speed CPU mode current consumption

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  • 5.4 Standard CPU mode current consumption

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    • Table 4. Standard CPU mode current consumption

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  • 5.5 I/O operating characteristics

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    • Table 5. I/O operating characteristics

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  • 5.6 Selected RF characteristics

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    • Table 6. Selected RF characteristics

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  • 5.7 Pin assignment

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    • Table 7. Pin assignment

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  • 5.8 Pin placement

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    • Figure 2. Pin placement

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  • 5.9 Layout drawing

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    • Figure 3. Layout drawing

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• 6 Hardware block diagram

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  • Figure 4. SPBT2632C2A.AT2 module block diagram

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• 7 Hardware design

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  • 7.1 Module reflow installation

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    • Table 8. Soldering

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    • Figure 5. Soldering profile

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  • 7.2 GPIO interface

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  • 7.3 UART interface

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    • Figure 6. Connection to host device

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    • Figure 7. Typical RS232 circuit

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  • 7.4 PCB layout guidelines

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    • Figure 8. PCB layout guidelines

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  • 7.5 Reset circuit

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    • 7.5.1 External reset circuit

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      • Figure 9. External reset circuit

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    • 7.5.2 Internal reset circuit

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      • Figure 10. Internal reset circuit

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  • 7.6 External LPO input circuit

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    • Table 9. System configuration variables

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    • Figure 11. External LPO circuit

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  • 7.7 Apple iOS CP reference design

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    • Figure 12. BT module

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    • Figure 13. Co-processor

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    • Figure 14. Power switch

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• 8 Regulatory compliance

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• 9 Ordering information

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  • Table 10. Ordering information

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• 10 Revision history

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  • Table 11. Document revision history

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