用户手册 — Microchip Technology IC MCU FLASH PIC16F676-I/ST TSSOP-14 MCP

目录

• High-Performance RISC CPU:

  3
• Special Microcontroller Features:

  3
• Low-Power Features:

  3
• Peripheral Features:

  3
• Pin Diagrams

  4
• Most Current Data Sheet

  5
• Errata

  5
• Customer Notification System

  5
• 1.0 Device Overview

  7
  • FIGURE 1-1: PIC16F630/676 block diagram

    7
  • TABLE 1-1: PIC16F630/676 Pinout Description

    8
• 2.0 Memory Organization

  9
  • 2.1 Program Memory Organization

    9
    • FIGURE 2-1: Program Memory Map and Stack for the PIC16F630/676

      9
  • 2.2 Data Memory Organization

    9
    • 2.2.1 General Purpose Register File

      9
    • 2.2.2 Special FUNCTION Registers

      10
      • FIGURE 2-2: Data Memory Map of the PIC16F630/676

        10
    • TABLE 2-1: PIC16F630/676 Special Registers Summary Bank 0

      11
    • TABLE 2-2: PIC16F630/676 Special Function Registers Summary Bank 1

      12
  • 2.3 PCL and PCLATH

    19
    • FIGURE 2-3: Loading Of PC In Different Situations

      19
    • 2.3.1 computed goto

      19
    • 2.3.2 Stack

      19
  • 2.4 Indirect Addressing, INDF and FSR Registers

    20
    • FIGURE 2-4: Direct/Indirect Addressing PIC16F630/676

      20
• 3.0 Ports A and C

  21
  • 3.1 PORTA and the TRISA Registers

    21
  • 3.2 Additional Pin Functions

    21
    • 3.2.1 Weak Pull-up

      21
    • 3.2.2 Interrupt-on-change

      22
    • 3.2.3 Pin Descriptions and Diagrams

      24
      • FIGURE 3-1: Block Diagram of RA0 and RA1 Pins

        24
      • FIGURE 3-2: Block Diagram of RA2

        25
      • FIGURE 3-3: Block Diagram of RA3

        25
      • FIGURE 3-4: Block Diagram of RA4

        26
      • FIGURE 3-5: Block Diagram of RA5

        26
      • TABLE 3-1: Summary of Registers Associated with PORTA

        27
  • 3.3 PORTC

    28
    • 3.3.1 RC0/AN4, RC1/AN5, RC2/AN6, RC3/ AN7

      28
      • FIGURE 3-6: BLOCK DIAGRAM OF RC0/RC1/RC2/RC3 PINs

        28
    • 3.3.2 RC4 and RC5

      28
      • FIGURE 3-7: BLOCK DIAGRAM OF RC4 AND RC5 PINS

        28
    • TABLE 3-2: Summary of Registers Associated with PORTC

      29
• 4.0 Timer0 Module

  31
  • 4.1 Timer0 Operation

    31
  • 4.2 Timer0 Interrupt

    31
    • FIGURE 4-1: Block Diagram of thE Timer0/WDT Prescaler

      31
  • 4.3 Using Timer0 with an External Clock

    32
  • 4.4 Prescaler

    33
    • 4.4.1 Switching Prescaler Assignment

      33
      • TABLE 4-1: Registers Associated with Timer0

        33
• 5.0 Timer1 Module with Gate Control

  34
  • FIGURE 5-1: TIMER1 BLOCK DIAGRAM

    34
  • 5.1 Timer1 Modes of Operation

    35
  • 5.2 Timer1 Interrupt

    35
  • 5.3 Timer1 Prescaler

    35
    • FIGURE 5-2: TIMER1 INCREMENTING EDGE

      35
  • 5.4 Timer1 Operation in Asynchronous Counter Mode

    37
    • 5.4.1 Reading and writing Timer1 in asynchronous counter mode

      37
  • 5.5 Timer1 Oscillator

    37
  • 5.6 Timer1 Operation During Sleep

    37
    • TABLE 5-1: Registers Associated with Timer1 as a Timer/Counter

      37
• 6.0 Comparator Module

  39
  • 6.1 Comparator Operation

    40
    • TABLE 6-1: Output state vs. input conditions

      40
    • FIGURE 6-1: Single Comparator

      40
  • 6.2 Comparator Configuration

    41
    • FIGURE 6-2: Comparator I/O operating Modes

      41
  • 6.3 Analog Input Connection Considerations

    42
    • FIGURE 6-3: Analog Input Mode

      42
  • 6.4 Comparator Output

    42
    • FIGURE 6-4: Modified Comparator Output Block Diagram

      42
  • 6.5 Comparator Reference

    43
    • 6.5.1 Configuring the Voltage Reference

      43
    • 6.5.2 Voltage Reference Accuracy/Error

      43
      • FIGURE 6-5: Comparator VOLTAGE REFERENCE BLOCK DIAGRAM

        43
  • 6.6 Comparator Response Time

    43
  • 6.7 Operation During Sleep

    43
  • 6.8 Effects of a Reset

    43
  • 6.9 Comparator Interrupts

    44
    • TABLE 6-2: Registers Associated with Comparator Module

      44
• 7.0 Analog-to-Digital Converter (A/D) Module (PIC16F676 only)

  45
  • FIGURE 7-1: A/D Block Diagram

    45
  • 7.1 A/D Configuration and Operation

    45
    • 7.1.1 Analog Port Pins

      45
    • 7.1.2 Channel Selection

      45
    • 7.1.3 Voltage Reference

      45
    • 7.1.4 Conversion Clock

      45
      • TABLE 7-1: Tad VS. DEVICE OPERATING FREQUENCIES

        46
    • 7.1.5 Starting a Conversion

      46
    • 7.1.6 Conversion Output

      46
      • FIGURE 7-2: 10-Bit A/D Result Format

        46
  • 7.2 A/D Acquisition Requirements

    49
    • FIGURE 7-3: Analog Input Model

      49
  • 7.3 A/D Operation During Sleep

    50
  • 7.4 Effects of Reset

    50
    • TABLE 7-2: Summary of A/D Registers

      50
• 8.0 Data EEPROM Memory

  51
  • 8.1 EEADR

    52
  • 8.2 EECON1 AND EECON2 REGISTERS

    52
  • 8.3 READING THE EEPROM DATA MEMORY

    53
  • 8.4 WRITING TO THE EEPROM DATA MEMORY

    53
  • 8.5 WRITE VERIFY

    53
    • 8.5.1 Using the data EEprom

      53
  • 8.6 PROTECTION AGAINST SPURIOUS WRITE

    53
  • 8.7 DATA EEPROM OPERATION DURING CODE-PROTECT

    54
    • TABLE 8-1: Registers/Bits Associated with Data EEPROM

      54
• 9.0 Special Features of the CPU

  55
  • 9.1 Configuration Bits

    56
  • 9.2 Oscillator Configurations

    57
    • 9.2.1 Oscillator Types

      57
    • 9.2.2 Crystal Oscillator / CERAmic Resonators

      57
      • FIGURE 9-1: Crystal Operation (or Ceramic Resonator) (HS, XT or LP Osc Configuration)

        57
      • FIGURE 9-2: External Clock Input Operation (HS, XT, EC, or LP Osc Configuration)

        57
      • TABLE 9-1: Capacitor Selection for Ceramic Resonators

        57
      • TABLE 9-2: Capacitor Selection for Crystal Oscillator

        57
    • 9.2.3 External Clock In

      58
    • 9.2.4 RC Oscillator

      58
      • FIGURE 9-3: RC OSCILLATOR MODE

        58
    • 9.2.5 Internal 4 MHz Oscillator

      58
    • 9.2.6 CLKOUT

      58
  • 9.3 Reset

    59
    • FIGURE 9-4: Simplified Block Diagram of On-chip Reset Circuit

      59
    • 9.3.1 MCLR

      60
      • FIGURE 9-5: Recommended MCLR Circuit

        60
    • 9.3.2 Power-On Reset (POR)

      60
    • 9.3.3 Power-up Timer (PWRT)

      60
    • 9.3.4 Oscillator Start-up Timer (OST)

      60
    • 9.3.5 Brown-out Detect (BOD)

      61
      • FIGURE 9-6: Brown-out Situations

        61
    • 9.3.6 Time-out Sequence

      61
    • 9.3.7 Power Control (PCON) Status Register

      61
      • TABLE 9-3: Time-out in Various Situations

        62
      • TABLE 9-4: Status/PCON Bits and Their Significance

        62
      • TABLE 9-5: Summary of Registers Associated with Brown-out

        62
      • TABLE 9-6: Initialization Condition for Special Registers

        62
      • TABLE 9-7: Initialization Condition for Registers

        63
      • FIGURE 9-7: Time-out Sequence on Power-up (MCLR not tied to Vdd): Case 1

        64
      • FIGURE 9-8: Time-out Sequence on Power-up (MCLR not tied to Vdd): Case 2

        64
      • FIGURE 9-9: Time-out Sequence on Power-up (MCLR tied to Vdd)

        64
  • 9.4 Interrupts

    65
    • FIGURE 9-10: INTERRUPT LOGIC

      66
    • 9.4.1 RA2/INT Interrupt

      67
    • 9.4.2 TMR0 Interrupt

      67
    • 9.4.3 PORTA Interrupt

      67
    • 9.4.4 Comparator Interrupt

      67
    • 9.4.5 A/D Converter Interrupt

      67
      • FIGURE 9-11: INT Pin Interrupt Timing

        67
      • TABLE 9-8: Summary of interrupt registers

        68
  • 9.5 Context Saving During Interrupts

    68
  • 9.6 Watchdog Timer (WDT)

    68
    • 9.6.1 WDT Period

      68
    • 9.6.2 WDT Programming Considerations

      68
      • FIGURE 9-12: Watchdog Timer Block Diagram

        69
      • TABLE 9-9: Summary of Watchdog Timer Registers

        69
  • 9.7 Power-Down Mode (Sleep)

    70
    • 9.7.1 Wake-up from SLEEP

      70
      • FIGURE 9-13: Wake-up from Sleep Through Interrupt

        70
  • 9.8 Code Protection

    71
  • 9.9 ID Locations

    71
  • 9.10 In-Circuit Serial Programming

    71
    • FIGURE 9-14: Typical In-Circuit Serial Programming Connection

      71
  • 9.11 In-Circuit Debugger

    71
    • TABLE 9-10: Debugger resources

      71
• 10.0 Instruction Set Summary

  73
  • 10.1 READ-MODIFY-WRITE OPERATIONS

    73
    • TABLE 10-1: Opcode Field Descriptions

      73
    • FIGURE 10-1: General Format for Instructions

      73
    • TABLE 10-2: PIC16F630/676 Instruction Set

      74
  • 10.2 Instruction Descriptions

    75
• 11.0 Development Support

  81
  • 11.1 MPLAB Integrated Development Environment Software

    81
  • 11.2 MPLAB C Compilers for Various Device Families

    82
  • 11.3 HI-TECH C for Various Device Families

    82
  • 11.4 MPASM Assembler

    82
  • 11.5 MPLINK Object Linker/ MPLIB Object Librarian

    82
  • 11.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    82
  • 11.7 MPLAB SIM Software Simulator

    83
  • 11.8 MPLAB REAL ICE In-Circuit Emulator System

    83
  • 11.9 MPLAB ICD 3 In-Circuit Debugger System

    83
  • 11.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    83
  • 11.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    84
  • 11.12 MPLAB PM3 Device Programmer

    84
  • 11.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    84
• 12.0 Electrical Specifications

  85
  • FIGURE 12-1: PIC16F630/676 With A/D Disabled Voltage-Frequency Graph, -40°C £ ta £ +125°C

    86
  • FIGURE 12-2: PIC16F676 With A/D Enabled Voltage-Frequency Graph, -40°C £ ta £ +125°C

    86
  • FIGURE 12-3: PIC16F676 With A/D Enabled Voltage-Frequency Graph, 0°C £ ta £ +125°C

    87
  • 12.1 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)

    88
  • 12.2 DC Characteristics: PIC16F630/676-I (Industrial)

    89
  • 12.3 DC Characteristics: PIC16F630/676-I (Industrial)

    90
  • 12.4 DC Characteristics: PIC16F630/676-E (Extended)

    91
  • 12.5 DC Characteristics: PIC16F630/676-E (Extended)

    92
  • 12.6 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)

    93
  • 12.7 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended) (Cont.)

    94
  • 12.8 Timing Parameter Symbology

    95
    • FIGURE 12-4: LOAD CONDITIONS

      95
  • 12.9 AC Characteristics: PIC16F630/676 (Industrial, Extended)

    96
    • FIGURE 12-5: External Clock Timing

      96
      • TABLE 12-1: External Clock Timing Requirements

        96
      • TABLE 12-2: pRECISION INTERNAL OSCILLATOR Parameters

        97
    • FIGURE 12-6: CLKOUT and I/O Timing

      98
      • TABLE 12-3: CLKOUT and I/O Timing Requirements

        98
    • FIGURE 12-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

      99
    • FIGURE 12-8: Brown-out Detect Timing and Characteristics

      99
      • TABLE 12-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Detect Requirements

        100
    • FIGURE 12-9: Timer0 and Timer1 External Clock Timings

      101
      • TABLE 12-5: Timer0 and Timer1 External Clock Requirements

        101
      • TABLE 12-6: Comparator Specifications

        102
      • TABLE 12-7: Comparator Voltage Reference Specifications

        102
      • TABLE 12-8: PIC16F676 A/D Converter Characteristics:

        103
    • FIGURE 12-10: PIC16F676 A/D Conversion Timing (Normal Mode)

      104
      • TABLE 12-9: PIC16F676 A/D Conversion Requirements

        104
    • FIGURE 12-11: PIC16F676 A/D Conversion Timing (Sleep Mode)

      105
      • TABLE 12-10: PIC16F676 A/D Conversion Requirements (SLEEP Mode)

        105
• 13.0 DC and AC Characteristics Graphs and Tables

  107
  • FIGURE 13-1: Typical Ipd vs. Vdd OVER TEMP (-40°C to +25°C)

    107
  • FIGURE 13-2: Typical Ipd vs. Vdd OVER TEMP (+85°C)

    107
  • FIGURE 13-3: Typical Ipd vs. Vdd OVER TEMP (+125°C)

    108
  • FIGURE 13-4: Maximum Ipd vs. Vdd OVER TEMP (-40°C to +25°C)

    108
  • FIGURE 13-5: Maximum Ipd vs. Vdd OVER TEMP (+85°C)

    109
  • FIGURE 13-6: Maximum Ipd vs. Vdd OVER TEMP (+125°C)

    109
  • FIGURE 13-7: Typical Ipd with BOD Enabled vs. Vdd Over Temp (-40°C to +125°C)

    110
  • FIGURE 13-8: Typical Ipd with CMP Enabled vs. Vdd Over Temp (-40°C to +125°C)

    110
  • FIGURE 13-9: Typical Ipd with A/D Enabled vs. Vdd Over Temp (-40°C to +25°C)

    111
  • FIGURE 13-10: Typical Ipd with A/D Enabled vs. Vdd Over Temp (+85°C)

    111
  • FIGURE 13-11: Typical Ipd with A/D Enabled vs. Vdd Over Temp (+125°C)

    112
  • FIGURE 13-12: Typical Ipd with T1 OSC Enabled vs. Vdd Over Temp (-40°C to +125°C), 32 kHz, C1 and C2=50 pF)

    112
  • FIGURE 13-13: Typical Ipd with CVref Enabled vs. Vdd Over Temp (-40°C to +125°C)

    113
  • FIGURE 13-14: Typical Ipd with WDT Enabled vs. Vdd Over Temp (-40°C to +125°C)

    113
  • FIGURE 13-15: MAXIMUM and MINIMUM INTOSC FREQ vs. Temperature with 0.1mF and 0.01mF decoupling (Vdd = 3.5V)

    114
  • FIGURE 13-16: MAXIMUM and MINIMUM INTOSC FREQ vs. Vdd with 0.1mF and 0.01mF decoupling (+25°C)

    114
  • FIGURE 13-17: Typical WDT Period vs. Vdd (-40°C to +125°C)

    115
• 14.0 Packaging Information

  117
  • 14.1 Package Marking Information

    117
  • 14.2 Package Details

    118
• Appendix A: Data Sheet Revision History

  123
  • Revision A

    123
  • Revision B

    123
  • Revision C

    123
  • Revision D

    123
  • Revision E (03/2007)

    123
  • Revision F (05/2010)

    123
• Appendix B: Device Differences

  123
  • TABLE B-1: Device Differences

    123
• Appendix C: Device Migrations

  124
• Appendix D: Migrating from other PIC® Devices

  124
• Index

  125
• The Microchip Web Site

  129
• Customer Change Notification Service

  129
• Customer Support

  129
• Reader Response

  130
• Product Identification System

  131
• Untitled

  132