用户手册目录About This Book55Before Using this Manual—Important Note55Audience55Organization56Suggested Reading59Conventions60Acronyms and Abbreviations61PowerPC Architecture Terminology Conventions64PartI Overview67Intended Audience67Contents67Conventions67Acronyms and Abbreviations68Chapter1 Overview711.1 Features711.2 MPC8260’s Architecture Overview741.2.1 MPC603e Core751.2.2 System Interface Unit (SIU)761.2.3 Communications Processor Module (CPM)761.3 Software Compatibility Issues771.3.1 Signals771.4 Differences between MPC860 and MPC8260791.5 Serial Protocol Table791.6 MPC8260 Configurations801.6.1 Pin Configurations801.6.2 Serial Performance801.7 MPC8260 Application Examples811.7.1 Examples of Communication Systems811.7.1.1 Remote Access Server811.7.1.2 Regional Office Router821.7.1.3 LAN-to-WAN Bridge Router831.7.1.4 Cellular Base Station841.7.1.5 Telecommunications Switch Controller841.7.1.6 SONET Transmission Controller851.7.2 Bus Configurations851.7.2.1 Basic System851.7.2.2 High-Performance Communication861.7.2.3 High-Performance System Microprocessor87Chapter2 PowerPC Processor Core892.1 Overview892.2 PowerPC Processor Core Features912.2.1 Instruction Unit932.2.2 Instruction Queue and Dispatch Unit932.2.3 Branch Processing Unit (BPU)942.2.4 Independent Execution Units942.2.4.1 Integer Unit (IU)942.2.4.2 Load/Store Unit (LSU)952.2.4.3 System Register Unit (SRU)952.2.5 Completion Unit952.2.6 Memory Subsystem Support962.2.6.1 Memory Management Units (MMUs)962.2.6.2 Cache Units962.3 Programming Model962.3.1 Register Set962.3.1.1 PowerPC Register Set972.3.1.2 MPC8260-Specific Registers992.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0)992.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)1022.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2)1032.3.1.2.4 Processor Version Register (PVR)1042.3.2 PowerPC Instruction Set and Addressing Modes1042.3.2.1 Calculating Effective Addresses1042.3.2.2 PowerPC Instruction Set1042.3.2.3 MPC8260 Implementation-Specific Instruction Set1062.4 Cache Implementation1062.4.1 PowerPC Cache Model1062.4.2 MPC8260 Implementation-Specific Cache Implementation1072.4.2.1 Data Cache1072.4.2.2 Instruction Cache1092.4.2.3 Cache Locking1092.4.2.3.1 Entire Cache Locking1092.4.2.3.2 Way Locking1092.5 Exception Model1102.5.1 PowerPC Exception Model1102.5.2 MPC8260 Implementation-Specific Exception Model1112.5.3 Exception Priorities1142.6 Memory Management1142.6.1 PowerPC MMU Model1152.6.2 MPC8260 Implementation-Specific MMU Features1162.7 Instruction Timing1172.8 Differences between the MPC8260’s Core and the PowerPC 603e Microprocessor118Chapter3 Memory Map121PartII Configuration and Reset135Audience135Contents135Suggested Reading135Conventions136Acronyms and Abbreviations136Chapter4 System Interface Unit (SIU)1394.1 System Configuration and Protection1404.1.1 Bus Monitor1414.1.2 Timers Clock1424.1.3 Time Counter (TMCNT)1424.1.4 Periodic Interrupt Timer (PIT)1434.1.5 Software Watchdog Timer1444.2 Interrupt Controller1454.2.1 Interrupt Configuration1464.2.2 Interrupt Source Priorities1474.2.2.1 SCC, FCC, and MCC Relative Priority1504.2.2.2 PIT, TMCNT, and IRQ Relative Priority1504.2.2.3 Highest Priority Interrupt1514.2.3 Masking Interrupt Sources1514.2.4 Interrupt Vector Generation and Calculation1524.2.4.1 Port C External Interrupts1544.3 Programming Model1554.3.1 Interrupt Controller Registers1554.3.1.1 SIU Interrupt Configuration Register (SICR)1554.3.1.2 SIU Interrupt Priority Register (SIPRR)1564.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)1574.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)1594.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)1604.3.1.6 SIU Interrupt Vector Register (SIVEC)1614.3.1.7 SIU External Interrupt Control Register (SIEXR)1624.3.2 System Configuration and Protection Registers1634.3.2.1 Bus Configuration Register (BCR)1634.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)1664.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)1664.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)1674.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)1684.3.2.6 SIU Module Configuration Register (SIUMCR)1694.3.2.7 Internal Memory Map Register (IMMR)1724.3.2.8 System Protection Control Register (SYPCR)1734.3.2.9 Software Service Register (SWSR)1744.3.2.10 60x Bus Transfer Error Status and Control Register1 (TESCR1)1744.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)1754.3.2.12 Local Bus Transfer Error Status and Control Register1 (L_TESCR1)1764.3.2.13 Local Bus Transfer Error Status and Control Register2 (L_TESCR2)1774.3.2.14 Time Counter Status and Control Register (TMCNTSC)1784.3.2.15 Time Counter Register (TMCNT)1794.3.2.16 Time Counter Alarm Register (TMCNTAL)1794.3.3 Periodic Interrupt Registers1804.3.3.1 Periodic Interrupt Status and Control Register (PISCR)1804.3.3.2 Periodic Interrupt Timer Count Register (PITC)1814.3.3.3 Periodic Interrupt Timer Register (PITR)1824.4 SIU Pin Multiplexing182Chapter5 Reset1855.1 Reset Causes1855.1.1 Reset Actions1865.1.2 Power-On Reset Flow1865.1.3 HRESET Flow1875.1.4 SRESET Flow1875.2 Reset Status Register (RSR)1885.3 Reset Mode Register (RMR)1895.4 Reset Configuration1905.4.1 Hard Reset Configuration Word1925.4.2 Hard Reset Configuration Examples1935.4.2.1 Single MPC8260 with Default Configuration1935.4.2.2 Single MPC8260 Configured from Boot EPROM1945.4.2.3 Multiple MPC8260s Configured from Boot EPROM1945.4.2.4 Multiple MPC8260s in a System with No EPROM196PartIII The Hardware Interface197Intended Audience197Contents197Suggested Reading198Conventions198Acronyms and Abbreviations199Chapter6 External Signals2036.1 Functional Pinout2036.2 Signal Descriptions204Chapter7 60x Signals2157.1 Signal Configuration2167.2 Signal Descriptions2177.2.1 Address Bus Arbitration Signals2177.2.1.1 Bus Request (BR)—Output2177.2.1.1.1 Address Bus Request (BR)—Output2177.2.1.1.2 Address Bus Request (BR)—Input2187.2.1.2 Bus Grant (BG)2187.2.1.2.1 Bus Grant (BG)—Input2187.2.1.2.2 Bus Grant (BG)—Output2197.2.1.3 Address Bus Busy (ABB)2197.2.1.3.1 Address Bus Busy (ABB)—Output2197.2.1.3.2 Address Bus Busy (ABB)—Input2207.2.2 Address Transfer Start Signal2207.2.2.1 Transfer Start (TS)2207.2.2.1.1 Transfer Start (TS)—Output2207.2.2.2 Transfer Start (TS)—Input2207.2.3 Address Transfer Signals2217.2.3.1 Address Bus (A[0–31])2217.2.3.1.1 Address Bus (A[0–31])—Output2217.2.3.1.2 Address Bus (A[0–31])—Input2217.2.4 Address Transfer Attribute Signals2217.2.4.1 Transfer Type (TT[0–4])2227.2.4.1.1 Transfer Type (TT[0–4])—Output2227.2.4.1.2 Transfer Type (TT[0–4])—Input2227.2.4.2 Transfer Size (TSIZ[0–3])2227.2.4.3 Transfer Burst (TBST)2227.2.4.4 Global (GBL)2237.2.4.4.1 Global (GBL)—Output2237.2.4.4.2 Global (GBL)—Input2237.2.4.5 Caching-Inhibited (CI)—Output2237.2.4.6 Write-Through (WT)—Output2237.2.5 Address Transfer Termination Signals2247.2.5.1 Address Acknowledge (AACK)2247.2.5.1.1 Address Acknowledge (AACK)—Output2247.2.5.1.2 Address Acknowledge (AACK)—Input2247.2.5.2 Address Retry (ARTRY)2257.2.5.2.1 Address Retry (ARTRY)—Output2257.2.5.2.2 Address Retry (ARTRY)—Input2257.2.6 Data Bus Arbitration Signals2267.2.6.1 Data Bus Grant (DBG)2267.2.6.1.1 Data Bus Grant (DBG)—Input2267.2.6.1.2 Data Bus Grant (DBG)—Output2267.2.6.2 Data Bus Busy (DBB)2277.2.6.2.1 Data Bus Busy (DBB)—Output2277.2.6.2.2 Data Bus Busy (DBB)—Input2277.2.7 Data Transfer Signals2277.2.7.1 Data Bus (D[0–63])2277.2.7.1.1 Data Bus (D[0–63])—Output2287.2.7.1.2 Data Bus (D[0–63])—Input2287.2.7.2 Data Bus Parity (DP[0–7])2287.2.7.2.1 Data Bus Parity (DP[0–7])—Output2287.2.7.2.2 Data Bus Parity (DP[0–7])—Input2297.2.8 Data Transfer Termination Signals2297.2.8.1 Transfer Acknowledge (TA)2297.2.8.1.1 Transfer Acknowledge (TA)—Input2297.2.8.1.2 Transfer Acknowledge (TA)—Output2307.2.8.2 Transfer Error Acknowledge (TEA)2307.2.8.2.1 Transfer Error Acknowledge (TEA)—Input2307.2.8.2.2 Transfer Error Acknowledge (TEA)—Output2317.2.8.3 Partial Data Valid Indication (PSDVAL)2317.2.8.3.1 Partial Data Valid (PSDVAL)—Input2317.2.8.3.2 Partial Data Valid (PSDVAL)—Output232Chapter8 The 60x Bus2338.1 Terminology2338.2 Bus Configuration2348.2.1 Single MPC8260 Bus Mode2348.2.2 60x-Compatible Bus Mode2358.3 60x Bus Protocol Overview2368.3.1 Arbitration Phase2378.3.2 Address Pipelining and Split-Bus Transactions2398.4 Address Tenure Operations2398.4.1 Address Arbitration2398.4.2 Address Pipelining2418.4.3 Address Transfer Attribute Signals2428.4.3.1 Transfer Type Signal (TT[0–4]) Encoding2428.4.3.2 Transfer Code Signals TC[0–2]2458.4.3.3 TBST and TSIZ[0–3] Signals and Size of Transfer2458.4.3.4 Burst Ordering During Data Transfers2468.4.3.5 Effect of Alignment on Data Transfers2468.4.3.6 Effect of Port Size on Data Transfers2488.4.3.7 60x-Compatible Bus Mode—Size Calculation2518.4.3.8 Extended Transfer Mode2528.4.4 Address Transfer Termination2558.4.4.1 Address Retried with ARTRY2558.4.4.2 Address Tenure Timing Configuration2578.4.5 Pipeline Control2588.5 Data Tenure Operations2588.5.1 Data Bus Arbitration2588.5.2 Data Streaming Mode2598.5.3 Data Bus Transfers and Normal Termination2598.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration2608.5.5 Port Size Data Bus Transfers and PSDVAL Termination2608.5.6 Data Bus Termination by Assertion of TEA2628.6 Memory Coherency—MEI Protocol2638.7 Processor State Signals2648.7.1 Support for the lwarx/stwcx. Instruction Pair2658.7.2 TLBISYNC Input2658.8 Little-Endian Mode265Chapter9 Clocks and Power Control2679.1 Clock Unit2679.2 Clock Configuration2689.3 External Clock Inputs2719.4 Main PLL2719.4.1 PLL Block Diagram2719.4.2 Skew Elimination2729.5 Clock Dividers2729.6 The MPC8260’s Internal Clock Signals2729.6.1 General System Clocks2739.7 PLL Pins2739.8 System Clock Control Register (SCCR)2749.9 System Clock Mode Register (SCMR)2759.10 Basic Power Structure276Chapter10 Memory Controller27710.1 Features27910.2 Basic Architecture28110.2.1 Address and Address Space Checking28410.2.2 Page Hit Checking28510.2.3 Error Checking and Correction (ECC)28510.2.4 Parity Generation and Checking28510.2.5 Transfer Error Acknowledge (TEA) Generation28510.2.6 Machine Check Interrupt (MCP) Generation28510.2.7 Data Buffer Controls (BCTLx)28610.2.8 Atomic Bus Operation28610.2.9 Data Pipelining28610.2.10 External Memory Controller Support28710.2.11 External Address Latch Enable Signal (ALE)28710.2.12 ECC/Parity Byte Select (PBSE)28710.2.13 Partial Data Valid Indication (PSDVAL)28810.3 Register Descriptions28910.3.1 Base Registers (BRx)29010.3.2 Option Registers (ORx)29210.3.3 60x SDRAM Mode Register (PSDMR)29710.3.4 Local Bus SDRAM Mode Register (LSDMR)30010.3.5 Machine A/B/C Mode Registers (MxMR)30210.3.6 Memory Data Register (MDR)30410.3.7 Memory Address Register (MAR)30510.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)30610.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)30610.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)30710.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)30810.3.12 Memory Refresh Timer Prescaler Register (MPTPR)30810.3.13 60x Bus Error Status and Control Registers (TESCRx)30910.3.14 Local Bus Error Status and Control Registers (L_TESCRx)30910.4 SDRAM Machine30910.4.1 Supported SDRAM Configurations31110.4.2 SDRAM Power-On Initialization31110.4.3 JEDEC-Standard SDRAM Interface Commands31110.4.4 Page-Mode Support and Pipeline Accesses31210.4.5 Bank Interleaving31210.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA)31310.4.6 SDRAM Device-Specific Parameters31410.4.6.1 Precharge-to-Activate Interval31410.4.6.2 Activate to Read/Write Interval31510.4.6.3 Column Address to First Data Out—CAS Latency31610.4.6.4 Last Data Out to Precharge31610.4.6.5 Last Data In to Precharge—Write Recovery31710.4.6.6 Refresh Recovery Interval (RFRC)31710.4.6.7 External Address Multiplexing Signal31710.4.6.8 External Address and Command Buffers (BUFCMD)31810.4.7 SDRAM Interface Timing31810.4.8 SDRAM Read/Write Transactions32210.4.9 SDRAM Mode-Set Command Timing32210.4.10 SDRAM Refresh32310.4.11 SDRAM Refresh Timing32310.4.12 SDRAM Configuration Examples32410.4.12.1 SDRAM Configuration Example (Page-Based Interleaving)32410.4.13 SDRAM Configuration Example (Bank-Based Interleaving)32610.5 General-Purpose Chip-Select Machine (GPCM)32710.5.1 Timing Configuration32810.5.1.1 Chip-Select Assertion Timing32910.5.1.2 Chip-Select and Write Enable Deassertion Timing33010.5.1.3 Relaxed Timing33110.5.1.4 Output Enable (OE) Timing33310.5.1.5 Programmable Wait State Configuration33310.5.1.6 Extended Hold Time on Read Accesses33310.5.2 External Access Termination33610.5.3 Boot Chip-Select Operation33710.5.4 Differences between MPC8xx’s GPCM and MPC8260’s GPCM33810.6 User-Programmable Machines (UPMs)33810.6.1 Requests34010.6.1.1 Memory Access Requests34110.6.1.2 UPM Refresh Timer Requests34110.6.1.3 Software Requests—run Command34210.6.1.4 Exception Requests34210.6.2 Programming the UPMs34210.6.3 Clock Timing34310.6.4 The RAM Array34510.6.4.1 RAM Words34610.6.4.1.1 Chip-Select Signals (CxTx)35010.6.4.1.2 Byte-Select Signals (BxTx)35110.6.4.1.3 General-Purpose Signals (GxTx, GOx)35210.6.4.1.4 Loop Control35210.6.4.1.5 Repeat Execution of Current RAM Word (REDO)35210.6.4.2 Address Multiplexing35310.6.4.3 Data Valid and Data Sample Control35310.6.4.4 Signals Negation35410.6.4.5 The Wait Mechanism35410.6.4.6 Extended Hold Time on Read Accesses35510.6.5 UPM DRAM Configuration Example35510.6.6 Differences between MPC8xx UPM and MPC8260 UPM35610.7 Memory System Interface Example Using UPM35710.7.0.1 EDO Interface Example36810.8 Handling Devices with Slow or Variable Access Times37610.8.1 Hierarchical Bus Interface Example37610.8.2 Slow Devices Example37610.9 External Master Support (60x-Compatible Mode)37710.9.1 60x-Compatible External Masters37710.9.2 MPC8260-Type External Masters37710.9.3 Extended Controls in 60x-Compatible Mode37710.9.4 Using BNKSEL SIgnals in Single-MPC8260 Bus Mode37810.9.5 Address Incrementing for External Bursting Masters37810.9.6 External Masters Timing37810.9.6.1 Example of External Master Using the SDRAM Machine380Chapter11 Secondary (L2) Cache Support38311.1 L2 Cache Configurations38311.1.1 Copy-Back Mode38311.1.2 Write-Through Mode38411.1.3 ECC/Parity Mode38611.2 L2 Cache Interface Parameters38911.3 System Requirements When Using the L2 Cache Interface38911.4 L2 Cache Operation38911.5 Timing Example390Chapter12 IEEE 1149.1 Test Access Port39312.1 Overview39312.2 TAP Controller39412.3 Boundary Scan Register39512.4 Instruction Register42012.5 MPC8260 Restrictions42212.6 Nonscan Chain Operation422PartIV Communications Processor Module423Intended Audience423Contents423Suggested Reading425Conventions426Acronyms and Abbreviations426Chapter13 Communications Processor Module Overview43113.1 Features43113.2 MPC8260 Serial Configurations43313.3 Communications Processor (CP)43413.3.1 Features43413.3.2 CP Block Diagram43413.3.3 PowerPC Core Interface43613.3.4 Peripheral Interface43613.3.5 Execution from RAM43713.3.6 RISC Controller Configuration Register (RCCR)43713.3.7 RISC Time-Stamp Control Register (RTSCR)43913.3.8 RISC Time-Stamp Register (RTSR)44013.3.9 RISC Microcode Revision Number44013.4 Command Set44113.4.1 CP Command Register (CPCR)44113.4.1.1 CP Commands44313.4.2 Command Register Example44513.4.3 Command Execution Latency44513.5 Dual-Port RAM44513.5.1 Buffer Descriptors (BDs)44713.5.2 Parameter RAM44713.6 RISC Timer Tables44813.6.1 RISC Timer Table Parameter RAM44913.6.2 RISC Timer Command Register (TM_CMD)45013.6.3 RISC Timer Table Entries45113.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)45113.6.5 set timer Command45213.6.6 RISC Timer Initialization Sequence45213.6.7 RISC Timer Initialization Example45213.6.8 RISC Timer Interrupt Handling45313.6.9 RISC Timer Table Scan Algorithm45313.6.10 Using the RISC Timers to Track CP Loading454Chapter14 Serial Interface with Time-Slot Assigner45514.1 Features45714.2 Overview45814.3 Enabling Connections to TSA46114.4 Serial Interface RAM46214.4.1 One Multiplexed Channel with Static Frames46314.4.2 One Multiplexed Channel with Dynamic Frames46314.4.3 Programming SIx RAM Entries46414.4.4 SIx RAM Programming Example46714.4.5 Static and Dynamic Routing46814.5 Serial Interface Registers47114.5.1 SI Global Mode Registers (SIxGMR)47114.5.2 SI Mode Registers (SIxMR)47114.5.3 SIx RAM Shadow Address Registers (SIxRSR)47714.5.4 SI Command Register (SIxCMDR)47814.5.5 SI Status Registers (SIxSTR)47914.6 Serial Interface IDL Interface Support47914.6.1 IDL Interface Example48014.6.2 IDL Interface Programming48314.7 Serial Interface GCI Support48514.7.1 SI GCI Activation/Deactivation Procedure48714.7.2 Serial Interface GCI Programming48714.7.2.1 Normal Mode GCI Programming48714.7.2.2 SCIT Programming487Chapter15 CPM Multiplexing49115.1 Features49215.2 Enabling Connections to TSA or NMSI49315.3 NMSI Configuration49415.4 CMX Registers49615.4.1 CMX UTOPIA Address Register (CMXUAR)49715.4.2 CMX SI1 Clock Route Register (CMXSI1CR)50015.4.3 CMX SI2 Clock Route Register (CMXSI2CR)50115.4.4 CMX FCC Clock Route Register (CMXFCR)50215.4.5 CMX SCC Clock Route Register (CMXSCR)50415.4.6 CMX SMC Clock Route Register (CMXSMR)507Chapter16 Baud-Rate Generators (BRGs)50916.1 BRG Configuration Registers 1–8 (BRGCx)51016.2 Autobaud Operation on a UART51216.3 UART Baud Rate Examples513Chapter17 Timers51517.1 Features51617.2 General-Purpose Timer Units51617.2.1 Cascaded Mode51717.2.2 Timer Global Configuration Registers (TGCR1 and TGCR2)51817.2.3 Timer Mode Registers (TMR1–TMR4)52017.2.4 Timer Reference Registers (TRR1–TRR4)52117.2.5 Timer Capture Registers (TCR1–TCR4)52217.2.6 Timer Counters (TCN1–TCN4)52217.2.7 Timer Event Registers (TER1–TER4)522Chapter18 SDMA Channels and IDMA Emulation52518.1 SDMA Bus Arbitration and Bus Transfers52618.2 SDMA Registers52718.2.1 SDMA Status Register (SDSR)52718.2.2 SDMA Mask Register (SDMR)52818.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA)52818.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)52818.3 IDMA Emulation52918.4 IDMA Features52918.5 IDMA Transfers53018.5.1 Memory-to-Memory Transfers53018.5.1.1 External Request Mode53218.5.1.2 Normal Mode53318.5.2 Memory to/from Peripheral Transfers53318.5.2.1 Dual-Address Transfers53418.5.2.1.1 Peripheral to Memory53418.5.2.1.2 Memory to Peripheral53418.5.2.2 Single Address (Fly-By) Transfers53518.5.2.2.1 Peripheral-to-Memory Fly-By Transfers53518.5.2.2.2 Memory-to-Peripheral Fly-By Transfers53518.5.3 Controlling 60x Bus Bandwidth53618.6 IDMA Priorities53618.7 IDMA Interface Signals53618.7.1 DREQx and DACKx53718.7.1.1 Level-Sensitive Mode53718.7.1.2 Edge-Sensitive Mode53718.7.2 DONEx53818.8 IDMA Operation53818.8.1 Auto Buffer and Buffer Chaining53918.8.2 IDMAx Parameter RAM54018.8.2.1 DMA Channel Mode (DCM)54218.8.2.2 Data Transfer Types as Programmed in DCM54418.8.2.3 Programming DTS and STS54418.8.3 IDMA Performance54618.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)54618.8.5 IDMA BDs54718.9 IDMA Commands55018.9.1 start_idma Command55018.9.2 stop_idma Command55018.10 IDMA Bus Exceptions55118.10.1 Externally Recognizing IDMA Operand Transfers55118.11 Programming the Parallel I/O Registers55218.12 IDMA Programming Examples55318.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)—IDMA255318.12.2 Memory-to-Peripheral Fly-By Mode (Both on 60x Bus)— IDMA3554Chapter19 Serial Communications Controllers (SCCs)55719.1 Features55819.1.1 The General SCC Mode Registers (GSMR1–GSMR4)55919.1.2 Protocol-Specific Mode Register (PSMR)56519.1.3 Data Synchronization Register (DSR)56519.1.4 Transmit-on-Demand Register (TODR)56519.2 SCC Buffer Descriptors (BDs)56619.3 SCC Parameter RAM56919.3.1 SCC Base Addresses57119.3.2 Function Code Registers (RFCR and TFCR)57119.3.3 Handling SCC Interrupts57219.3.4 Initializing the SCCs57319.3.5 Controlling SCC Timing with RTS, CTS, and CD57419.3.5.1 Synchronous Protocols57419.3.5.2 Asynchronous Protocols57719.3.6 Digital Phase-Locked Loop (DPLL) Operation57819.3.6.1 Encoding Data with a DPLL58019.3.7 Clock Glitch Detection58219.3.8 Reconfiguring the SCCs58219.3.8.1 General Reconfiguration Sequence for an SCC Transmitter58219.3.8.2 Reset Sequence for an SCC Transmitter58319.3.8.3 General Reconfiguration Sequence for an SCC Receiver58319.3.8.4 Reset Sequence for an SCC Receiver58319.3.8.5 Switching Protocols58319.3.9 Saving Power583Chapter20 SCC UART Mode58520.1 Features58620.2 Normal Asynchronous Mode58720.3 Synchronous Mode58720.4 SCC UART Parameter RAM58820.5 Data-Handling Methods: Character- or Message- Based58920.6 Error and Status Reporting59020.7 SCC UART Commands59020.8 Multidrop Systems and Address Recognition59120.9 Receiving Control Characters59220.10 Hunt Mode (Receiver)59420.11 Inserting Control Characters into the Transmit Data Stream59420.12 Sending a Break (Transmitter)59520.13 Sending a Preamble (Transmitter)59520.14 Fractional Stop Bits (Transmitter)59520.15 Handling Errors in the SCC UART Controller59620.16 UART Mode Register (PSMR)59720.17 SCC UART Receive Buffer Descriptor (RxBD)59920.18 SCC UART Transmit Buffer Descriptor (TxBD)60220.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)60320.20 SCC UART Status Register (SCCS)60520.21 SCC UART Programming Example60620.22 S-Records Loader Application607Chapter21 SCC HDLC Mode60921.1 SCC HDLC Features61021.2 SCC HDLC Channel Frame Transmission61021.3 SCC HDLC Channel Frame Reception61121.4 SCC HDLC Parameter RAM61121.5 Programming the SCC in HDLC Mode61321.6 SCC HDLC Commands61321.7 Handling Errors in the SCC HDLC Controller61421.8 HDLC Mode Register (PSMR)61521.9 SCC HDLC Receive Buffer Descriptor (RxBD)61621.10 SCC HDLC Transmit Buffer Descriptor (TxBD)61921.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)62021.12 SCC HDLC Status Register (SCCS)62221.13 SCC HDLC Programming Examples62221.13.1 SCC HDLC Programming Example #162321.13.2 SCC HDLC Programming Example #262421.14 HDLC Bus Mode with Collision Detection62521.14.1 HDLC Bus Features62721.14.2 Accessing the HDLC Bus62721.14.3 Increasing Performance62821.14.4 Delayed RTS Mode62921.14.5 Using the Time-Slot Assigner (TSA)63021.14.6 HDLC Bus Protocol Programming63121.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol63121.14.6.2 HDLC Bus Controller Programming Example631Chapter22 SCC BISYNC Mode63322.1 Features63422.2 SCC BISYNC Channel Frame Transmission63422.3 SCC BISYNC Channel Frame Reception63522.4 SCC BISYNC Parameter RAM63522.5 SCC BISYNC Commands63722.6 SCC BISYNC Control Character Recognition63822.7 BISYNC SYNC Register (BSYNC)63922.8 SCC BISYNC DLE Register (BDLE)64022.9 Sending and Receiving the Synchronization Sequence64122.10 Handling Errors in the SCC BISYNC64122.11 BISYNC Mode Register (PSMR)64222.12 SCC BISYNC Receive BD (RxBD)64422.13 SCC BISYNC Transmit BD (TxBD)64622.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)64722.15 SCC Status Registers (SCCS)64822.16 Programming the SCC BISYNC Controller64922.17 SCC BISYNC Programming Example650Chapter23 SCC Transparent Mode65323.1 Features65323.2 SCC Transparent Channel Frame Transmission Process65423.3 SCC Transparent Channel Frame Reception Process65423.4 Achieving Synchronization in Transparent Mode65523.4.1 Synchronization in NMSI Mode65523.4.1.1 In-Line Synchronization Pattern65523.4.1.2 External Synchronization Signals65623.4.1.2.1 External Synchronization Example65623.4.1.3 Transparent Mode without Explicit Synchronization65723.4.2 Synchronization and the TSA65723.4.2.1 Inline Synchronization Pattern65823.4.2.2 Inherent Synchronization65823.4.3 End of Frame Detection65823.5 CRC Calculation in Transparent Mode65823.6 SCC Transparent Parameter RAM65823.7 SCC Transparent Commands65923.8 Handling Errors in the Transparent Controller66023.9 Transparent Mode and the PSMR66123.10 SCC Transparent Receive Buffer Descriptor (RxBD)66123.11 SCC Transparent Transmit Buffer Descriptor (TxBD)66223.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)66423.13 SCC Status Register in Transparent Mode (SCCS)66523.14 SCC2 Transparent Programming Example665Chapter24 SCC Ethernet Mode66924.1 Ethernet on the MPC826067024.2 Features67124.3 Connecting the MPC8260 to Ethernet67224.4 SCC Ethernet Channel Frame Transmission67324.5 SCC Ethernet Channel Frame Reception67424.6 The Content-Addressable Memory (CAM) Interface67524.7 SCC Ethernet Parameter RAM67624.8 Programming the Ethernet Controller67824.9 SCC Ethernet Commands67824.10 SCC Ethernet Address Recognition67924.11 Hash Table Algorithm68124.12 Interpacket Gap Time68124.13 Handling Collisions68124.14 Internal and External Loopback68224.15 Full-Duplex Ethernet Support68224.16 Handling Errors in the Ethernet Controller68224.17 Ethernet Mode Register (PSMR)68324.18 SCC Ethernet Receive BD68524.19 SCC Ethernet Transmit Buffer Descriptor68724.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)68924.21 SCC Ethernet Programming Example691Chapter25 SCC AppleTalk Mode69325.1 Operating the LocalTalk Bus69325.2 Features69425.3 Connecting to AppleTalk69525.4 Programming the SCC in AppleTalk Mode69525.4.1 Programming the GSMR69525.4.2 Programming the PSMR69625.4.3 Programming the TODR69625.4.4 SCC AppleTalk Programming Example696Chapter26 Serial Management Controllers (SMCs)69726.1 Features69826.2 Common SMC Settings and Configurations69926.2.1 SMC Mode Registers (SMCMR1/SMCMR2)69926.2.2 SMC Buffer Descriptor Operation70126.2.3 SMC Parameter RAM70226.2.3.1 SMC Function Code Registers (RFCR/TFCR)70426.2.4 Disabling SMCs On-the-Fly70526.2.4.1 SMC Transmitter Full Sequence70526.2.4.2 SMC Transmitter Shortcut Sequence70526.2.4.3 SMC Receiver Full Sequence70526.2.4.4 SMC Receiver Shortcut Sequence70626.2.4.5 Switching Protocols70626.2.5 Saving Power70626.2.6 Handling Interrupts in the SMC70626.3 SMC in UART Mode70626.3.1 Features70726.3.2 SMC UART Channel Transmission Process70726.3.3 SMC UART Channel Reception Process70826.3.4 Programming the SMC UART Controller70826.3.5 SMC UART Transmit and Receive Commands70826.3.6 Sending a Break70926.3.7 Sending a Preamble70926.3.8 Handling Errors in the SMC UART Controller70926.3.9 SMC UART RxBD71026.3.10 SMC UART TxBD71226.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)71426.3.12 SMC UART Controller Programming Example71526.4 SMC in Transparent Mode71626.4.1 Features71726.4.2 SMC Transparent Channel Transmission Process71726.4.3 SMC Transparent Channel Reception Process71826.4.4 Using SMSYN for Synchronization71826.4.5 Using the Time-Slot Assigner (TSA) for Synchronization71926.4.6 SMC Transparent Commands72126.4.7 Handling Errors in the SMC Transparent Controller72126.4.8 SMC Transparent RxBD72226.4.9 SMC Transparent TxBD72326.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)72426.4.11 SMC Transparent NMSI Programming Example72526.5 The SMC in GCI Mode72626.5.1 SMC GCI Parameter RAM72626.5.2 Handling the GCI Monitor Channel72726.5.2.1 SMC GCI Monitor Channel Transmission Process72726.5.2.2 SMC GCI Monitor Channel Reception Process72726.5.3 Handling the GCI C/I Channel72726.5.3.1 SMC GCI C/I Channel Transmission Process72726.5.3.2 SMC GCI C/I Channel Reception Process72726.5.4 SMC GCI Commands72826.5.5 SMC GCI Monitor Channel RxBD72826.5.6 SMC GCI Monitor Channel TxBD72826.5.7 SMC GCI C/I Channel RxBD72926.5.8 SMC GCI C/I Channel TxBD72926.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)730Chapter27 Multi-Channel Controllers (MCCs)73127.1 Features73127.2 MCC Data Structure Organization73227.3 Global MCC Parameters73327.4 Channel Extra Parameters73527.5 Super-Channel Table73527.6 Channel-Specific HDLC Parameters73827.6.1 Internal Transmitter State (TSTATE)73927.6.2 Interrupt Mask (INTMSK)73927.6.3 Channel Mode Register (CHAMR)74027.6.4 Internal Receiver State (RSTATE)74127.7 Channel-Specific Transparent Parameters74227.7.1 Channel Mode Register (CHAMR)—Transparent Mode74327.8 MCC Configuration Registers (MCCFx)74527.9 MCC Commands74627.10 MCC Exceptions74727.10.1 MCC Event Register (MCCE)/Mask Register (MCCM)74827.10.1.1 Interrupt Table Entry74927.11 MCC Buffer Descriptors75127.11.1 Receive Buffer Descriptor (RxBD)75127.11.2 Transmit Buffer Descriptor (TxBD)75327.12 MCC Initialization and Start/Stop Sequence75427.12.1 Single-Channel Initialization75527.12.2 Super Channel Initialization75627.13 MCC Latency and Performance756Chapter28 Fast Communications Controllers (FCCs)75928.1 Overview76028.2 General FCC Mode Registers (GFMRx)76128.3 FCC Protocol-Specific Mode Registers (FPSMRx)76528.4 FCC Data Synchronization Registers (FDSRx)76528.5 FCC Transmit-on-Demand Registers (FTODRx)76528.6 FCC Buffer Descriptors76628.7 FCC Parameter RAM76828.7.1 FCC Function Code Registers (FCRx)77128.8 Interrupts from the FCCs77128.8.1 FCC Event Registers (FCCEx)77228.8.2 FCC Mask Registers (FCCMx)77228.8.3 FCC Status Registers (FCCSx)77228.9 FCC Initialization77228.10 FCC Interrupt Handling77328.11 FCC Timing Control77328.12 Disabling the FCCs On-the-Fly77728.12.1 FCC Transmitter Full Sequence77828.12.2 FCC Transmitter Shortcut Sequence77828.12.3 FCC Receiver Full Sequence77828.12.4 FCC Receiver Shortcut Sequence77928.12.5 Switching Protocols77928.13 Saving Power779Chapter29 ATM Controller78129.1 Features78229.2 ATM Controller Overview78429.2.1 Transmitter Overview78529.2.1.1 AAL5 Transmitter Overview78529.2.1.2 AAL1 Transmitter Overview78529.2.1.3 AAL0 Transmitter Overview78629.2.1.4 Transmit External Rate and Internal Rate Modes78629.2.2 Receiver Overview78629.2.2.1 AAL5 Receiver Overview78729.2.2.2 AAL1 Receiver Overview78729.2.2.3 AAL0 Receiver Overview78829.2.3 Performance Monitoring78829.2.4 ABR Flow Control78829.3 ATM Pace Control (APC) Unit78829.3.1 APC Modes and ATM Service Types78829.3.2 APC Unit Scheduling Mechanism78929.3.3 Determining the Scheduling Table Size79029.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table79029.3.3.2 Determining the Number of Slots in a Scheduling Table79129.3.4 Determining the Time-Slot Scheduling Rate of a Channel79129.3.5 ATM Traffic Type79129.3.5.1 Peak Cell Rate Traffic Type79129.3.5.2 Determining the PCR Traffic Type Parameters79129.3.5.3 Peak and Sustain Traffic Type (VBR)79229.3.5.3.1 Example for Using VBR Traffic Parameters79229.3.5.3.2 Handling the Cell Loss Priority (CLP)—VBR Type 1 and 279329.3.5.4 Peak and Minimum Cell Rate Traffic Type (UBR+)79329.3.6 Determining the Priority of an ATM Channel79329.4 VCI/VPI Address Lookup Mechanism79429.4.1 External CAM Lookup79429.4.2 Address Compression79529.4.2.1 VP-Level Address Compression Table (VPLT)79729.4.2.2 VC-Level Address Compression Tables (VCLTs)79829.4.3 Misinserted Cells79829.4.4 Receive Raw Cell Queue79929.5 Available Bit Rate (ABR) Flow Control80029.5.1 The ABR Model80029.5.1.1 ABR Flow Control Source End-System Behavior80129.5.1.2 ABR Flow Control Destination End-System Behavior80129.5.1.3 ABR Flowcharts80229.5.2 RM Cell Structure80529.5.2.1 RM Cell Rate Representation80629.5.3 ABR Flow Control Setup80729.6 OAM Support80729.6.1 ATM-Layer OAM Definitions80729.6.2 Virtual Path (F4) Flow Mechanism80829.6.3 Virtual Channel (F5) Flow Mechanism80829.6.4 Receiving OAM F4 or F5 Cells80829.6.5 Transmitting OAM F4 or F5 Cells80929.6.6 Performance Monitoring80929.6.6.1 Running a Performance Block Test81029.6.6.2 PM Block Monitoring81029.6.6.3 PM Block Generation81129.6.6.4 BRC Performance Calculations81229.7 User-Defined Cells (UDC)81229.7.1 UDC Extended Address Mode (UEAD)81329.8 ATM Layer Statistics81329.9 ATM-to-TDM Interworking81429.9.1 Automatic Data Forwarding81429.9.2 Using Interrupts in Automatic Data Forwarding81529.9.3 Timing Issues81629.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)81629.9.5 Mapping TDM Time Slots to VCs81629.9.6 CAS Support81629.9.7 Trunk Condition81729.9.8 ATM-to-ATM Data Forwarding81729.10 ATM Memory Structure81729.10.1 Parameter RAM81729.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only)82029.10.1.2 VCI Filtering (VCIF)82029.10.1.3 Global Mode Entry (GMODE)82129.10.2 Connection Tables (RCT, TCT, and TCTE)82129.10.2.1 ATM Channel Code82229.10.2.2 Receive Connection Table (RCT)82329.10.2.2.1 AAL5 Protocol-Specific RCT82629.10.2.2.2 AAL5-ABR Protocol-Specific RCT82729.10.2.2.3 AAL1 Protocol-Specific RCT82829.10.2.2.4 AAL0 Protocol-Specific RCT83029.10.2.3 Transmit Connection Table (TCT)83129.10.2.3.1 AAL5 Protocol-Specific TCT83429.10.2.3.2 AAL1 Protocol-Specific TCT83429.10.2.3.3 AAL0 Protocol-Specific TCT83529.10.2.3.4 VBR Protocol-Specific TCTE83629.10.2.3.5 UBR+ Protocol-Specific TCTE83729.10.2.3.6 ABR Protocol-Specific TCTE83829.10.3 OAM Performance Monitoring Tables84029.10.4 APC Data Structure84129.10.4.1 APC Parameter Tables84229.10.4.2 APC Priority Table84329.10.4.3 APC Scheduling Tables84329.10.5 ATM Controller Buffer Descriptors (BDs)84429.10.5.1 Transmit Buffer Operations84429.10.5.2 Receive Buffers Operation84529.10.5.2.1 Static Buffer Allocation84529.10.5.2.2 Global Buffer Allocation84629.10.5.2.3 Free Buffer Pools84729.10.5.2.4 Free Buffer Pool Parameter Tables84829.10.5.3 ATM Controller Buffers84929.10.5.4 AAL5 RxBD84929.10.5.5 AAL1 RxBD85129.10.5.6 AAL0 RxBD85229.10.5.7 AAL5, AAL1 User-Defined Cell—RxBD Extension85329.10.5.8 AAL5 TxBDs85429.10.5.9 AAL1 TxBDs85629.10.5.10 AAL0 TxBDs85729.10.5.11 AAL5, AAL1 User-Defined Cell—TxBD Extension85829.10.6 AAL1 Sequence Number (SN) Protection Table (AAL1 Only)85829.10.7 UNI Statistics Table85829.11 ATM Exceptions85929.11.1 Interrupt Queues85929.11.2 Interrupt Queue Entry86029.11.3 Interrupt Queue Parameter Tables86129.12 The UTOPIA Interface86229.12.1 UTOPIA Interface Master Mode86229.12.1.1 UTOPIA Master Multiple PHY Operation86329.12.2 UTOPIA Interface Slave Mode86329.12.2.1 UTOPIA Slave Multiple PHY Operation86429.12.2.2 UTOPIA Clocking Modes86429.12.2.3 UTOPIA Loop-Back Modes86529.13 ATM Registers86529.13.1 General FCC Mode Register (GFMR)86529.13.2 FCC Protocol-Specific Mode Register (FPSMR)86529.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)86729.13.4 FCC Transmit Internal Rate Registers (FTIRRx)86829.14 ATM Transmit Command87029.15 SRTS Generation and Clock Recovery Using External Logic87129.16 Configuring the ATM Controller for Maximum CPM Performance87229.16.1 Using Transmit Internal Rate Mode87229.16.2 APC Configuration87329.16.3 Buffer Configuration873Chapter30 Fast Ethernet Controller87530.1 Fast Ethernet on the MPC826087630.2 Features87730.3 Connecting the MPC8260 to Fast Ethernet87830.4 Ethernet Channel Frame Transmission87930.5 Ethernet Channel Frame Reception88130.6 Flow Control88230.7 CAM Interface88230.8 Ethernet Parameter RAM88330.9 Programming Model88630.10 Ethernet Command Set88630.11 RMON Support88830.12 Ethernet Address Recognition88930.13 Hash Table Algorithm89130.14 Interpacket Gap Time89230.15 Handling Collisions89230.16 Internal and External Loopback89230.17 Ethernet Error-Handling Procedure89330.18 Fast Ethernet Registers89330.18.1 FCC Ethernet Mode Register (FPSMR)89430.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)89530.19 Ethernet RxBDs89730.20 Ethernet TxBDs900Chapter31 FCC HDLC Controller90331.1 Key Features90431.2 HDLC Channel Frame Transmission Processing90431.3 HDLC Channel Frame Reception Processing90531.4 HDLC Parameter RAM90631.5 Programming Model90731.5.1 HDLC Command Set90731.5.2 HDLC Error Handling90831.6 HDLC Mode Register (FPSMR)90931.7 HDLC Receive Buffer Descriptor (RxBD)91131.8 HDLC Transmit Buffer Descriptor (TxBD)91431.9 HDLC Event Register (FCCE)/Mask Register (FCCM)91631.10 FCC Status Register (FCCS)918Chapter32 FCC Transparent Controller92132.1 Features92232.2 Transparent Channel Operation92232.3 Achieving Synchronization in Transparent Mode92232.3.1 In-Line Synchronization Pattern92332.3.2 External Synchronization Signals92332.3.3 Transparent Synchronization Example924Chapter33 Serial Peripheral Interface (SPI)92533.1 Features92633.2 SPI Clocking and Signal Functions92633.3 Configuring the SPI Controller92733.3.1 The SPI as a Master Device92733.3.2 The SPI as a Slave Device92833.3.3 The SPI in Multimaster Operation92833.4 Programming the SPI Registers93033.4.1 SPI Mode Register (SPMODE)93033.4.1.1 SPI Examples with Different SPMODE[LEN] Values93233.4.2 SPI Event/Mask Registers (SPIE/SPIM)93333.4.3 SPI Command Register (SPCOM)93333.5 SPI Parameter RAM93433.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)93633.6 SPI Commands93633.7 The SPI Buffer Descriptor (BD) Table93733.7.1 SPI Buffer Descriptors (BDs)93733.7.1.1 SPI Receive BD (RxBD)93833.7.1.2 SPI Transmit BD (TxBD)93933.8 SPI Master Programming Example94033.9 SPI Slave Programming Example94133.10 Handling Interrupts in the SPI942Chapter34 I2C Controller94334.1 Features94434.2 I2C Controller Clocking and Signal Functions94434.3 I2C Controller Transfers94534.3.1 I2C Master Write (Slave Read)94634.3.2 I2C Loopback Testing94634.3.3 I2C Master Read (Slave Write)94634.3.4 I2C Multi-Master Considerations94734.4 I2C Registers94834.4.1 I2C Mode Register (I2MOD)94834.4.2 I2C Address Register (I2ADD)94934.4.3 I2C Baud Rate Generator Register (I2BRG)94934.4.4 I2C Event/Mask Registers (I2CER/I2CMR)95034.4.5 I2C Command Register (I2COM)95034.5 I2C Parameter RAM95134.6 I2C Commands95334.7 The I2C Buffer Descriptor (BD) Table95434.7.1 I2C Buffer Descriptors (BDs)95434.7.1.1 I2C Receive Buffer Descriptor (RxBD)95534.7.1.2 I2C Transmit Buffer Descriptor (TxBD)956Chapter35 Parallel I/O Ports95735.1 Features95735.2 Port Registers95835.2.1 Port Open-Drain Registers (PODRA–PODRD)95835.2.2 Port Data Registers (PDATA–PDATD)95835.2.3 Port Data Direction Registers (PDIRA–PDIRD)95935.2.4 Port Pin Assignment Register (PPAR)96035.2.5 Port Special Options Registers A–D (PSORA–PSORD)96035.3 Port Block Diagram96235.4 Port Pins Functions96235.4.1 General Purpose I/O Pins96335.4.2 Dedicated Pins96335.5 Ports Tables96335.6 Interrupts from Port C975A.1 PowerPC Registers—User Registers977A.2 PowerPC Registers—Supervisor Registers978A.3 MPC8260-Specific SPRs979文件大小: 9.9 MB页数: 1006Language: English打开用户手册