用户手册 — National Instruments 6023E

目录

• 6023E/6024E/6025E User Manual

  1
• Support

  2
  • Worldwide Technical Support and Product Information

    2
  • National Instruments Corporate Headquarters

    2
  • Worldwide Offices

    2
• Important Information

  3
  • Warranty

    3
  • Copyright

    3
  • Trademarks

    3
  • WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

    3
• Contents

  4
• About This Manual

  9
  • Conventions Used in This Manual

    9
  • Related Documentation

    10
• Chapter 1 Introduction

  11
  • Features of the 6023E, 6024E, and 6025E

    11
  • Using PXI with CompactPCI

    12
  • What You Need to Get Started

    12
  • Software Programming Choices

    13
    • National Instruments Application Software

      13
    • NIDAQ Driver Software

      14
  • Optional Equipment

    15
• Chapter 2 Installation and Configuration

  17
  • Software Installation

    17
  • Unpacking

    17
  • Hardware Installation

    18
  • Hardware Configuration

    19
• Chapter 3 Hardware Overview

  20
  • Analog Input

    21
    • Input Mode

      21
    • Input Range

      22
    • Dithering

      23
    • Multichannel Scanning Considerations

      24
  • Analog Output

    25
    • Analog Output Glitch

      25
  • Digital I/O

    26
  • Timing Signal Routing

    26
    • Programmable Function Inputs

      27
    • Device and RTSI Clocks

      28
    • RTSI Triggers

      28
• Chapter 4 Signal Connections

  31
  • I/O Connector

    31
  • Analog Input Signal Overview

    38
    • Types of Signal Sources

      38
      • Floating Signal Sources

        39
      • GroundReferenced Signal Sources

        39
    • Analog Input Modes

      39
  • Analog Input Signal Connections

    41
    • Differential Connection Considerations (DIFF Input Configuration)

      43
      • Differential Connections for GroundReferenced Signal Sources

        44
      • Differential Connections for Nonreferenced or Floating Signal Sources

        45
    • SingleEnded Connection Considerations

      47
      • SingleEnded Connections for Floating Signal Sources (RSEConfiguration)

        48
      • SingleEnded Connections for Grounded Signal Sources (NRSEConfiguration)

        48
    • CommonMode Signal Rejection Considerations

      49
  • Analog Output Signal Connections

    49
  • Digital I/O Signal Connections

    50
    • All Devices

      50
  • Programmable Peripheral Interface (PPI)

    52
    • Port C Pin Assignments

      53
    • Power-up State

      54
      • Changing DIO Power-up State to Pulled Low

        54
    • Timing Specifications

      55
    • Mode 1 Input Timing

      57
    • Mode 1 Output Timing

      58
    • Mode 2 Bidirectional Timing

      59
  • Power Connections

    60
  • Timing Connections

    60
    • Programmable Function Input Connections

      61
    • DAQ Timing Connections

      62
      • SCANCLK Signal

        63
      • EXTSTROBE* Signal

        63
      • TRIG1 Signal

        64
      • TRIG2 Signal

        65
      • STARTSCAN Signal

        66
      • CONVERT* Signal

        68
      • AIGATE Signal

        69
      • SISOURCE Signal

        70
    • Waveform Generation Timing Connections

      70
      • WFTRIG Signal

        70
      • UPDATE* Signal

        71
      • UISOURCE Signal

        72
    • GeneralPurpose Timing Signal Connections

      73
      • GPCTR0_SOURCE Signal

        73
      • GPCTR0_GATE Signal

        74
      • GPCTR0_OUT Signal

        75
      • GPCTR0_UP_DOWN Signal

        75
      • GPCTR1_SOURCE Signal

        76
      • GPCTR1_GATE Signal

        76
      • GPCTR1_OUT Signal

        77
      • GPCTR1_UP_DOWN Signal

        77
      • FREQ_OUT Signal

        79
  • Field Wiring Considerations

    79
• Chapter 5 Calibration

  80
  • Loading Calibration Constants

    80
  • SelfCalibration

    81
  • External Calibration

    81
  • Other Considerations

    82
• Appendix A Specifications

  83
• Appendix B Custom Cabling and Optional Connectors

  101
• Appendix C Common Questions

  107
• Appendix D Technical Support Resources

  112
• Glossary

  114
  • Numbers/Symbols

    114
  • A-B

    115
  • C-D

    116
  • E

    117
  • F-G

    118
  • H-I

    119
  • K-M

    120
  • N-P

    121
  • Q-R

    122
  • S

    123
  • T-U

    124
  • V

    125
  • W

    126
• Index

  127
  • Numbers

    127
  • A

    127
  • B-C

    128
  • D-E

    129
  • F-H

    130
  • I-O

    131
  • P

    132
  • Q-S

    133
  • T

    135
  • U-W

    136
• Figures

  7
  • Figure 1-1. The Relationship Between the Programming Environment, NI-DAQ, and Your Hardware

    15
  • Figure 3-1. PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E Block Diagram

    20
  • Figure 3-2. DAQCard-6024E Block Diagram

    21
  • Figure 3-3. Dithering

    24
  • Figure 3-4. CONVERT* Signal Routing

    27
  • Figure 3-5. PCI RTSI Bus Signal Connection

    29
  • Figure 3-6. PXI RTSI Bus Signal Connection

    30
  • Figure 4-1. I/O Connector Pin Assignment for the 6023E/6024E

    32
  • Figure 4-2. I/O Connector Pin Assignment for the 6025E

    33
  • Figure 4-3. Programmable Gain Instrumentation Amplifier (PGIA)

    40
  • Figure 4-4. Summary of Analog Input Connections

    42
  • Figure 4-5. Differential Input Connections for Ground Referenced Signals

    44
  • Figure 4-6. Differential Input Connections for Nonreferenced Signals

    45
  • Figure 4-7. Single Ended Input Connections for Nonreferenced or Floating Signals

    48
  • Figure 4-8. Single Ended Input Connections for Ground Referenced Signals

    49
  • Figure 4-9. Analog Output Connections

    50
  • Figure 4-10. Digital I/O Connections

    51
  • Figure 4-11. Digital I/O Connections Block Diagram

    52
  • Figure 4-12. DIO Channel Configured for High DIO Power-up State with External Load

    54
  • Figure 4-13. Timing Specifications for Mode 1 Input Transfer

    57
  • Figure 4-14. Timing Specifications for Mode 1 Output Transfer

    58
  • Figure 4-15. Timing Specifications for Mode 2 Bidirectional Transfer

    59
  • Figure 4-16. Timing I/O Connections

    61
  • Figure 4-17. Typical Posttriggered Acquisition

    62
  • Figure 4-18. Typical Pretriggered Acquisition

    63
  • Figure 4-19. SCANCLK Signal Timing

    63
  • Figure 4-20. EXTSTROBE* Signal Timing

    64
  • Figure 4-21. TRIG1 Input Signal Timing

    64
  • Figure 4-22. TRIG1 Output Signal Timing

    65
  • Figure 4-23. TRIG2 Input Signal Timing

    66
  • Figure 4-24. TRIG2 Output Signal Timing

    66
  • Figure 4-25. STARTSCAN Input Signal Timing

    67
  • Figure 4-26. STARTSCAN Output Signal Timing

    67
  • Figure 4-27. CONVERT* Input Signal Timing

    68
  • Figure 4-28. CONVERT* Output Signal Timing

    69
  • Figure 4-29. SISOURCE Signal Timing

    70
  • Figure 4-30. WFTRIG Input Signal Timing

    71
  • Figure 4-31. WFTRIG Output Signal Timing

    71
  • Figure 4-32. UPDATE* Input Signal Timing

    72
  • Figure 4-33. UPDATE* Output Signal Timing

    72
  • Figure 4-34. UISOURCE Signal Timing

    73
  • Figure 4-35. GPCTR0_SOURCE Signal Timing

    74
  • Figure 4-36. GPCTR0_GATE Signal Timing in Edge Detection Mode

    75
  • Figure 4-37. GPCTR0_OUT Signal Timing

    75
  • Figure 4-38. GPCTR1_SOURCE Signal Timing

    76
  • Figure 4-39. GPCTR1_GATE Signal Timing in Edge Detection Mode

    77
  • Figure 4-40. GPCTR1_OUT Signal Timing

    77
  • Figure 4-41. GPCTR Timing Summary

    78
  • Figure B-1. 68 Pin E Series Connector Pin Assignments

    103
  • Figure B-2. 68 Pin Extended Digital Input Connector Pin Assignments

    104
  • Figure B-3. 50 Pin E Series Connector Pin Assignments

    105
  • Figure B-4. 50-Pin Extended Digital Input Connector Pin Assignments

    106
• Tables

  8
  • Table 3-1. Available Input Configurations

    22
  • Table 3-2. Measurement Precision

    22
  • Table 3-3. Pins Used by PXI E Series Device

    30
  • Table 4-1. I/O Connector Details

    31
  • Table 4-2. I/O Connector Signal Descriptions

    34
  • Table 4-3. I/O Signal Summary

    37
  • Table 4-4. Port C Signal Assignments

    53
  • Table 4-5. Signal Names Used in Timing Diagrams

    55